MC68711E20CFNE3 Freescale Semiconductor, MC68711E20CFNE3 Datasheet - Page 82

• Manufacturer Part Number: MC68711E20CFNE3
• Description: IC MCU 8BIT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68711E20CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: M687xx
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPR1 and SPR0 — SPI Clock Rate Select Bits
7.7.2 SPI Status Register
SPIF — SPI Transfer Complete Flag
WCOL — Write Collision Bit
Bit 5 — Not implemented
MODF — Mode Fault Bit
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When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master
device has a steady state low value. When CPOL is set, SCK idles high. Refer to
Clock Phase and Polarity
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPHA bit selects one of two different clocking protocols. Refer to
and
These two serial peripheral rate bits select one of four baud rates to be used as SCK if the device is a
master; however, they have no effect in the slave mode.
SPIF is set upon completion of data transfer between the processor and the external device. If SPIF
goes high, and if SPIE is set, a serial peripheral interrupt is generated. To clear the SPIF bit, read the
SPSR with SPIF set, then access the SPDR. Unless SPSR is read (with SPIF set) first, attempts to
write SPDR are inhibited.
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an access
of SPDR. Refer to
Always reads 0.
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to
Select (SS)
0 = No write collision
1 = Write collision
0 = No mode fault
1 = Mode fault
7.4 Clock Phase and Polarity
Address:
Reset:
and
Read:
Write:
7.6 SPI System
7.5.4 Slave Select (SS)
$0029
SPIF
Bit 7
0
and SPR0
SPR1
Controls.
0 0
0 1
1 0
1 1
WCOL
Figure 7-4. SPI Status Register (SPSR)
6
0
Errors.
MC68HC711D3 Data Sheet, Rev. 2.1
Controls.
Table 7-1. SPI Clock Rates
5
0
0
Divide By
E Clock
16
32
and
2
4
MODF
7.6 SPI System
4
0
3
0
0
E = 2 MHz (Baud)
Frequency at
62.5 kHz
1.0 MHz
500 kHz
125 kHz
Errors.
2
0
0
1
0
0
Freescale Semiconductor
Figure 7-2
Bit 0
0
0
Figure 7-2
7.5.4 Slave
and
7.4