MAX6882ETE+ Maxim Integrated Products, MAX6882ETE+ Datasheet - Page 13

• Manufacturer Part Number: MAX6882ETE+
• Description: IC SEQUENCE/SUPERVISOR 16TQFN
• Manufacturer: Maxim Integrated Products
• Type: Sequencerr

Specifications of MAX6882ETE+

• Number Of Voltages Monitored: 2
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Monitored Voltage: - 0.3 V to + 6 V
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 1100 uA
• Maximum Power Dissipation: 1349 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

reference ramp voltage. During ramp down, if an OUT_
voltage is greater than the reference ramp voltage by
more than V
control ramp voltage from decreasing until the slow
OUT_ voltage catches up. If an OUT_ voltage is greater
or less than the reference ramp voltage by more than
V
is initiated. In fast-shutdown mode, a 100Ω pulldown
resistor is connected from OUT_ to GND to quickly dis-
charge capacitance at OUT_, and GATE_ is pulled low
with a strong I
Figure 4 shows the aborted sequencing mode. When
EN/UV goes low before t
puts go low, and the device goes into fast shutdown.
To ensure that the OUT_ voltages are not held high by
a large output capacitance after a fault has occurred,
there is a 100Ω internal pulldown at OUT_. The pull-
down ensures that all OUT_ voltages are below V
(referenced to GND) before power-up cycling is initiat-
ed. The internal pulldown also ensures a fast discharge
of the output capacitor during fast shutdown and fault
modes. The pulldowns are not present during normal
operation.
No external compensation is required for sequencing
or slew-rate control.
The highest voltage on IN1, IN2, or IN3 supplies power
to the device. The undervoltage threshold for each IN_
supply is set with an external resistor-divider from each
IN_ to SET_ to ground. To disable sequencing on any
IN_, connect IN_ to ground (or leave unconnected) and
connect SET_ to a voltage greater than 0.5V.
The MAX6880/MAX6881 feature three and the MAX6882/
MAX6883 feature two externally adjustable IN_ under-
voltage lockout thresholds (SET1/SET2/SET3). The 0.5V
SET_ threshold enables monitoring IN_ voltages as low
as 0.5V. The undervoltage threshold for each IN_ sup-
ply is set with an external resistor-divider from each IN_
to SET_ to ground (see Figure 6). All SET_ inputs must
be above the internal SET_ threshold (0.5V) to enable
sequencing functionality. Use the following formula to
set the UVLO threshold:
where V
V
TRK_F
TH
is the 500mV SET threshold.
Undervoltage Lockout Threshold Inputs (SET_)
, a fault is signaled and the fast-shutdown mode
IN_
TRK
is the undervoltage lockout threshold and
GDS
V
, the control loop dynamically stops the
IN_
______________________________________________________________________________________
current (see Figure 3).
= V
TH
TIMEOUT
(R1 + R2) / R2
Stability Comment
Dual-/Triple-Voltage, Power-Supply
Internal Pulldown
expires, all the out-
IN1/IN2/IN3
Inputs
TH_PL
Sequencers/Supervisors
MARGIN allows system-level testing while power sup-
plies are below the normal ranges as adjusted by the
SET_ inputs. Drive MARGIN low before varying system
voltages below the adjusted thresholds to avoid signal-
ing an error. The state of PG/RST does not change
while MARGIN is low. PG/RST and all monitoring func-
tions are disabled while MARGIN is low. MARGIN
makes it possible to vary the supplies without a need to
adjust the thresholds to prevent sequencer alerts. Drive
MARGIN high or leave it unconnected for normal oper-
ating mode.
The reference ramp voltage slew rate during any con-
trolled power-up/down phase can be programmed in
the 90V/s to 950V/s range by connecting a capacitor
(C
mula to calculate the typical slew rate:
where slew rate is in V/s and C
The capacitor at C
od (t
For example, if C
350ms, t
example, if C
rate = 93.5V/s.
C
large enough so the parasitic PC board capacitance is
negligible. C
C
Figure 6. Setting the Undervoltage (UVLO) Thresholds
SLEW
SLEW
SLEW
RETRY
< 1nF.
) from SLEW to ground. Use the following for-
is the capacitor on SLEW pad, and must be
Margin Input
V
IN_
FAULT
), see Table 1.
Slew Rate = (9.35 x 10
SLEW
SLEW
R2
R1
= 21.91ms, slew rate = 935V/s. For
SLEW
SLEW
should be in the range of 100pF <
= 1nF, we have t
Slew-Rate Control Input (SLEW)
(M M A A R R G G I I N N ) (MAX6880/MAX6882)
IN_
SET_
also sets the retry timeout peri-
= 100pF, we have t
MAX6880–
MAX6883
SLEW
-8
)/ C
is in farads.
RETRY
SLEW
= 3.5s, slew
RETRY
13
=