MAX6882ETE+ Maxim Integrated Products, MAX6882ETE+ Datasheet - Page 14

• Manufacturer Part Number: MAX6882ETE+
• Description: IC SEQUENCE/SUPERVISOR 16TQFN
• Manufacturer: Maxim Integrated Products
• Type: Sequencerr

Specifications of MAX6882ETE+

• Number Of Voltages Monitored: 2
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Monitored Voltage: - 0.3 V to + 6 V
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 1100 uA
• Maximum Power Dissipation: 1349 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. C
The capacitor (C
OUT_ slew rate, thus controlling the inrush current
required to charge the load capacitor at OUT_. Using
the programmed slew rate, limit the inrush current by
using the following formula:
where I
is in V/s.
To adjust the desired delay period (t
sequencing is enabled, connect a capacitor (C
between DELAY to ground (see Figures 2 to 5). The
selected delay time is also enforced when EN/UV rises
from low to high when all the input voltages are present.
Use the following formula to calculate the delay time:
where t
DELAY unconnected for the default 200µs delay.
These devices feature a PG/RST timeout period.
Connect a capacitor (C
ground to program the PG/RST timeout period. After all
OUT_ outputs exceed their IN_ referenced thresholds
(V
period t
where t
Leave TIMEOUT unconnected for the default 200µs
timeout delay.
Drive logic EN/UV input above V
sequencing during power-up operation. Drive logic
EN/UV below V
operation. Connect EN/UV to an external resistor-
divider network to set the external undervoltage lockout
threshold.
Dual-/Triple-Voltage, Power-Supply
Sequencers/Supervisors
14
TH_PG
______________________________________________________________________________________
INRUSH
t
DELAY
TIMEOUT
TIME PERIOD
TIMEOUT
TIMEOUT
), PG/RST remains low for the selected timeout
t
Slew Rate
DELAY
t
t
RETRY
FAULT
SLEW
is in µs and C
is in amperes, C
EN_F
(see Figure 3).
SLEW
= 200µs + (500kΩ x C
= 200µs + (500kΩ x C
I
INRUSH
is in µs and C
Timing Formulas
Timeout Period Input (TIMEOUT)
) at SLEW to ground, controls the
to initiate tracking power-down
= C
TIMEOUT
Logic-Enable Input (EN/U U V V )
Delay Time Input (DELAY)
OUT
DELAY
Limiting Inrush Current
OUT
EN_R
TIMEOUT
(9.35 x 10
(MAX6880/MAX6882)
3.506 x 10
2.191 x 10
x SR
) from TIMEOUT to
is in farads, and SR
is in farads. Leave
FORMULAS
to initiate voltage
DELAY
TIMEOUT
DELAY
-8
9
8
is in farads.
) / C
x C
x C
)
SLEW
SLEW
SLEW
) before
)
DELAY
)
ABP powers the analog circuitry. Bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. ABP takes the highest voltage of
IN_. Do not use ABP to provide power to external cir-
cuitry. ABP maintains the device supply voltage during
rapid power-down conditions.
The MAX6880/MAX6881 monitor three OUT_ and the
MAX6882/MAX6883 monitor two OUT_ outputs to con-
trol the sequencing performance. After the internal sup-
ply (ABP) exceeds the minimum voltage (2.7V)
requirements, EN/UV > V
greater than their adjusted SET_ thresholds, OUT1/
OUT2/OUT3 begin to sequence.
During fault conditions, an internal pulldown resistor
(100Ω) on OUT_ is enabled to help discharge load
capacitance (100Ω is connected for fast power-down
control).
The MAX6880–MAX6883 feature up to three GATE_ out-
puts to drive up to three external n-channel FET gates.
The following conditions must be met before GATE_
begins enhancing the external n-channel FET_:
1) All SET_ inputs (SET1/SET2/SET3) are above their
2) At least one IN_ input is above the minimum operat-
3) EN/UV > 1.25V.
At power-up mode, GATE_ voltages are enhanced by
control loops so all OUT_ voltages sequence at a
capacitor-adjusted slew rate. Each GATE_ is internally
pulled up to 5V above its relative IN_ voltage to fully
enhance the external n-channel FET when power-up is
complete.
The MAX6880/MAX6882 include a power-good (PG/RST)
output. PG/RST is an open-drain output and requires an
external pullup resistor.
All the OUT_ outputs must exceed their IN_ referenced
thresholds (IN_ x V
period t
tion) before PG/RST asserts high. PG/RST stays low for
the selected reset timeout period (t
the OUT_ voltages exceed their IN_ referenced thresh-
olds. PG/RST goes low when V
V
Power-Good Output (PG/RST) (MAX6880/MAX6882)
EN_R
0.5V thresholds.
ing voltage (2.7V).
(see Figure 2).
TIMEOUT
(see the TIMEOUT Period Input sec-
TH_PG
ABP Input (MAX6880/MAX6882)
) for the selected reset timeout
EN_R
, and IN1/IN2/IN3 are all
SET_
OUT1/OUT2/OUT3
< V
TIMEOUT
TH
or V
Outputs
) after all
EN/UV
GATE_
<