MAX16031ETM+ Maxim Integrated Products, MAX16031ETM+ Datasheet - Page 32

• Manufacturer Part Number: MAX16031ETM+
• Description: IC SYSTEM MON EEPROM 48-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Multi-Voltage Supervisorr

Specifications of MAX16031ETM+

• Number Of Voltages Monitored: 8
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 8 Selectable Threshold Combinations
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.9 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 2222.2 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EEPROM-Based System Monitors
with Nonvolatile Fault Memory
The MAX16031/MAX16032 feature an I
patible 2-wire (SDA and SCL) serial interface for com-
munication with a master device. All possible
communication formats are shown in Figure 5. The
slave address and SMBALERT# are described further
in the following subsections. Figure 1 shows a detailed
2-wire interface timing diagram. For descriptions of the
I
I
Management Bus (SMBus) Specification Version 2.0.
The MAX16031/MAX16032 allow 2-wire communication
up to 400kHz. SDA and SCL require external pullup
resistors.
The slave address inputs, A0 and A1, are each capa-
ble of detecting three different states, allowing nine
identical devices to share the same serial bus. Connect
A0 and A1 to GND, DBP, or leave as not connected
(N.C.). See Table 15 for a listing of all possible 7-bit
address input connections and their corresponding
serial-bus addresses.
Table 13. Fault Log EEPROM
32
2
2
C and SMBus protocol and terminology, refer to the
C-Bus Specification Version 2.1 and the System
REGISTER
ADDRESS
______________________________________________________________________________________
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C/SMBus-Compatible Serial Interface
ADDRESS
MEMORY
EEPROM
8Ah
8Bh
8Ch
8Dh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Eh
RANGE
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
BIT
2
Slave Address
Copy of r51h[7:0] at the time the fault log was triggered.
Copy of r52h[7:0] at the time the fault log was triggered.
Copy of r53h[7:0] at the time the fault log was triggered.
IN1 conversion result at the time the fault log was triggered.
IN2 conversion result at the time the fault log was triggered. 8 MSBs only.
IN3 conversion result at the time the fault log was triggered. 8 MSBs only.
IN4 conversion result at the time the fault log was triggered. 8 MSBs only.
IN5 conversion result at the time the fault log was triggered. 8 MSBs only.
IN6 conversion result at the time the fault log was triggered. 8 MSBs only.
IN7 conversion result at the time the fault log was triggered. 8 MSBs only.
IN8 conversion result at the time the fault log was triggered. 8 MSBs only.
Internal temperature sensor conversion result at the time the fault log was triggered.
8 MSBs from 10-bit ADC conversion.
Remote temperature sensor 1 conversion result at the time the fault log was triggered.
8 MSBs from 10-bit ADC conversion.
Remote temperature sensor 2 conversion result at the time the fault log was triggered.
8 MSBs from 10-bit ADC conversion.
Current-sense conversion result at the time the fault log was triggered.
C/SMBus-com-
SMBALERT# is an optional interrupt signal defined in
Appendix A of the SMBus Specification. The
MAX16031/MAX16032 provide output ALERT as this
interrupt signal. If enabled, ALERT asserts if any one of
the following outputs asserts: FAULT1, FAULT2,
RESET, OVERT, or OVERC. Additionally, if a GPIO_ is
configured for a fault output, a fault at this output also
causes ALERT to assert. ALERT deasserts when all
fault conditions are removed (i.e., when all fault outputs
are high).
Typically ALERT is connected to all other SMBALERT#
open-drain signals in the system, creating a wired-OR
function with all SMBALERT# outputs. When the master
is interrupted by its SMBALERT# input, it stops or fin-
ishes the current bus transfer and places an alert
response address (ARA) on the bus. The slave that
pulled the SMBALERT# signal low acknowledges the
ARA and places its own address on the bus, identifying
itself to the master as the slave that caused the inter-
rupt. The 7-bit ARA is ‘0001100’ and the R/W bit is a
don’t care.
DESCRIPTION
SMBALERT#