MAX16031ETM+ Maxim Integrated Products, MAX16031ETM+ Datasheet - Page 35

• Manufacturer Part Number: MAX16031ETM+
• Description: IC SYSTEM MON EEPROM 48-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Multi-Voltage Supervisorr

Specifications of MAX16031ETM+

• Number Of Voltages Monitored: 8
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 8 Selectable Threshold Combinations
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.9 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 2222.2 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX16031/MAX16032 provide software reboot and
fault log commands. A software reboot initiates the
boot-up sequence, which normally occurs at POR.
During boot-up, EEPROM configuration data is copied
to registers. To initiate a software reboot, send 0xFC
using the send byte format. A software-initiated fault log
is functionally the same as a hardware-initiated fault
log. During a fault log, ADC registers and fault informa-
tion are logged in EEPROM. To trigger a software initi-
ated fault log, send 0xFD using the send byte format.
Table 14. Miscellaneous Settings (continued)
Table 15. Setting the I
Address
REGISTER
ADDRESS
5Ch
5Eh
5Fh
GND
GND
GND
N.C.
N.C.
N.C.
DBP
DBP
DBP
A1
ADDRESS
MEMORY
EEPROM
______________________________________________________________________________________
DCh
DEh
DFh
GND
GND
GND
N.C.
DBP
N.C.
DBP
N.C.
DBP
A0
2
C/SMBus Slave
RANGE
[7:0]
[7:2]
BIT
[6]
[7]
[0]
[1]
Special Commands
EEPROM-Based System Monitors
BUS ADDRESS
Consecutive Faults on Primary Thresholds:
0 = Fault occurs after primary threshold is exceeded one time (normal operation).
1 = Fault occurs after primary threshold is exceeded twice.
Fault Log ADC Conversions Option:
0 = When a fault log is triggered, only fault flags are saved in EEPROM.
1 = When a fault log is triggered, fault flags and ADC conversion results (8 MSBs) are
saved in EEPROM.
Firmware Version. 8 bits of memory for user-defined firmware version number.
Configuration Lock:
Write a ‘1’ to r5Fh[0] to toggle this register bit.
0 = Register and EEPROM configuration unlocked.
1 = Register and EEPROM configuration locked.
Fault Log EEPROM Lock Flag (set automatically after fault log is triggered):
Write a ‘1’ to r5Fh[1] to toggle this register bit.
0 = EEPROM is not locked. A triggered fault log stores fault information to EEPROM.
1 = A fault log has been triggered. Write a ‘1’ to this bit to clear the flag and allow a
new fault log to be triggered.
Not used.
with Nonvolatile Fault Memory
0011000
0011001
0011010
0101001
0101010
0101011
1001100
1001111
1001110
The MAX16031/MAX16032 contain an IEEE 1149.1- com-
pliant JTAG port in addition to the I
serial bus. Either interface may be used to access internal
memory; however, only one interface is allowed to run at
a time. All digital I/Os on the MAX16031/MAX16032 are
IEEE 1149.1 boundary-scan compliant, and contain the
typical JTAG boundary scan cells that allow the
inputs/outputs to be polled or forced high/low using stan-
dard JTAG instructions. The MAX16031/MAX16032 con-
tain extra JTAG instructions and registers not included in
the JTAG specification that provide access to internal
memory. The extra instructions are: LOAD ADDRESS,
WRITE, READ, REBOOT, SAVE, and USERCODE. The
extra registers are: memory address, memory write,
memory read, and user-code data. See Figure 6 for a
block diagram of the JTAG interface.
The TAP controller is a finite state machine that
responds to the logic level at TMS on the rising edge of
TCK. See Figure 7 for a diagram of the finite state
machine.
Test-Logic-Reset: At power-up, the TAP controller is in
the test-logic-reset state. The instruction register con-
tains the IDCODE instruction. All system logic of the
device operates normally.
Test Access Port (TAP) Controller State Machine
DESCRIPTION
JTAG Serial Interface
2
C/SMBus-compatible
35