MAX16031ETM+ Maxim Integrated Products, MAX16031ETM+ Datasheet - Page 36

• Manufacturer Part Number: MAX16031ETM+
• Description: IC SYSTEM MON EEPROM 48-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Multi-Voltage Supervisorr

Specifications of MAX16031ETM+

• Number Of Voltages Monitored: 8
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 8 Selectable Threshold Combinations
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.9 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 2222.2 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Run-Test/Idle: The run-test/idle state is used between
scan operations or during specific tests. The instruction
register and test data registers remain idle.
Select-DR-Scan: All test data registers retain their pre-
vious state. With TMS low, a rising edge of TCK moves
the controller into the capture-DR state and initiates a
scan sequence. TMS high during a rising edge on TCK
moves the controller to the select-IR-scan state.
Capture-DR: Data are parallel-loaded into the test data
registers selected by the current instruction. If the instruc-
tion does not call for a parallel load or the selected test
data register does not allow parallel loads, the test data
register remains at its current value. On the rising edge of
TCK, the controller goes to the shift-DR state if TMS is low
or it goes to the exit1-DR state if TMS is high.
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Figure 6. JTAG Block Diagram
36
______________________________________________________________________________________
TMS
TCK
TDI
R
PU
V
DBP
MEMORY ADDRESS REGISTER
BOUNDARY SCAN REGISTER
MEMORY WRITE REGISTER
IDENTIFICATION REGISTER
MEMORY READ REGISTER
INSTRUCTION REGISTER
USER CODE REGISTER
[LENGTH = 198 BITS]
TEST ACCESS PORT
(TAP) CONTROLLER
[LENGTH = 32 BITS]
[LENGTH = 32 BITS]
[LENGTH = 8 BITS]
[LENGTH = 8 BITS]
[LENGTH = 8 BITS]
BYPASS REGISTER
[LENGTH = 5 BITS]
[LENGTH = 1 BIT]
AND EEPROM
REGISTERS
Shift-DR: The test data register selected by the current
instruction is connected between TDI and TDO and
shifts data one stage toward its serial output on each
rising edge of TCK while TMS is low. On the rising edge
of TCK, the controller goes to the exit1-DR state if TMS
is high.
Exit1-DR: While in this state, a rising edge on TCK puts
the controller in the update-DR state. A rising edge on
TCK with TMS low puts the controller in the pause-DR
state.
Pause-DR: Shifting of the test data registers is halted
while in this state. All test data registers retain their pre-
vious state. The controller remains in this state while
TMS is low. A rising edge on TCK with TMS high puts
the controller in the exit2-DR state.
01101
01100
01010
01001
01000
00001
00010
00100
00000
11111
MUX 1
COMMAND
DECODER
MUX 2
01101
01100
SAVE
REBOOT
TDO