BD3951F-E2 Rohm Semiconductor, BD3951F-E2 Datasheet - Page 7

• Manufacturer Part Number: BD3951F-E2
• Description: IC REG LDO W/VOLT DETECT 8SOP
• Manufacturer: Rohm Semiconductor

Specifications of BD3951F-E2

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: 6 ~ 20 V
• Voltage - Dropout (typical): 0.31V @ 100mA
• Number Of Regulators: 1
• Current - Output: 150mA (Min)
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOP
• Primary Input Voltage: 13.5V
• Output Voltage: 5.1V
• Dropout Voltage Vdo: 310mV
• No. Of Pins: 8
• Output Current: 150mA
• Voltage Regulator Case Style: SOP
• Operating Temperature Range: -40°C To +125°C
• Svhc: No
• Mounting Style: SMD/SMT
• Output Voltage Fixed: 5.1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

●Notes for use
BD3951F
© 2009 ROHM Co., Ltd. All rights reserved.
www.rohm.com
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This product are produced with strict quality control, but might be destroyed in using beyond absolute maximum ratings.
The destroyed IC failure mode cannot be defined (like Short mode, or Open mode).
Therefore physical safety guard, like fuse, is recommended to prevent unexpected extreme condition which might
beyond absolute maximum ratings.
BD3951F can operate within the operating supply voltage range and operating temperature range.
The Limits over the input voltage is not warranted, however electric characteristics curve in operating condition should
be within the expected linearity.
GND terminal voltage must be always forced with the lowest voltage among the terminals.
Power GND pattern and Small signal GND pattern should be separated each other and is recommended to supply one
point GND on the board to eliminate the surge current influences. External components GND pattern should not be
long to avoid electrical interferences.
For thermal design, refer to the thermal de-rating characteristics and be sure to use this IC within the power dissipation
range at any conditions.
Short circuits among the output terminals and short circuits between output terminals and VCC/GND terminal due to
metallic foreign particles would result in permanent damage to the device. And this IC’s Pin Assignment is 1pin=Vcc,
5pin=GND. So if this IC is mounted upside down, the device damaged permanently due to the huge current from GND
pin to Vcc pin.
The extent electromagnetic condition might cause wrong operation of BD3951F.
Note that running set testing procedure using capacitors connected to low-impedance terminals may produce stress on
the IC. Therefore, be certain to use proper discharge procedure before each process of the Testing. To prevent
electrostatic stress in the assembly process, thoroughly ground yourself and any equipment that could sustain ESD
potential, and continue observing ESD-prevention procedures in all handling, transfer and storage operations. Before
attempting to any component to the test system, make certain that the power supply is OFF. Likewise, be sure to turn
the power supply OFF before removing any component connected to the test system.
This IC is a Monolithic IC which has P+ isolation in the P substrate. A P-N junction is formed from this P layer and the
N layer produces various types of parasitic devices. Fig. 18 shows parasitic devices around resistor and NPN transistor.
f lower voltages than GND level are applied for A and B terminals, parasitic Di (P-N junction) would ON in both resistor
and NPN transistor examples.
Moreover, in above condition, parasitic NPN transistor which is formed with parasitic Di and adjoined N layer would ON
in NPN transistor example. Parasitic devices are inevitable in the structure of the IC. The operation of parasitic devices
can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly, you
must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P
substrate) voltage to an input pin.
（Terminal A）
（Terminal A）
N
P
＋
P layer
Resistor
GND
N
GND
P
Parasitic
Parasitic
Fig.18 Bipolar Transistor
P
＋
N
7/9
（Terminal B）
(Terminal B）
Adjoined N layer
N
Parasitic
P
＋
C
NPN Transistor
P layer
N
B
B
P
GND
E
E
C
GND
Parasitic
P
＋
N
Technical Note
2009.07 - Rev.A