AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 614
AT91SAM7S64C-AU
Manufacturer Part Number
AT91SAM7S64C-AU
Description
IC ARM7 MCU 32BIT 64K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7S16-MU.pdf
(779 pages)
Specifications of AT91SAM7S64C-AU
Package / Case
64-LQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
55MHz
Number Of I /o
32
Core Processor
ARM7
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, SPI, SSC, UART/USART, USB
Core Size
16/32-Bit
Core
ARM7TDMI
Package
64LQFP
Device Core
ARM7TDMI
Family Name
AT91
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
32
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7S64B-AU::AT91SAM7S64B-AU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7S64C-AU
Manufacturer:
ATMEL
Quantity:
4 300
Part Number:
AT91SAM7S64C-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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40.6.2.6
40.6.2.7
40.6.2.8
40.6.2.9
40.6.2.10
614
AT91SAM7S Series Preliminary
ADC: GOVRE Bit is not Set when Reading CDR
ADC: GOVRE Bit is not Set when Disabling a Channel
ADC: OVRE Flag Behavior
ADC: EOC Set although Channel Disabled
ADC: Spurious Clear of EOC Flag
None
When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on
channel “x” with the following conditions:
GOVRE should be set but is not.
None
When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x]
and DRDY being already active, GOVRE does not rise.
Note:
None
When the OVRE flag (on channel i) has been set but the related EOC status (of channel i) has
been cleared (by a read of CDRi or LCDR), reading the Status register at the same instant as an
end of conversion (causing the set of EOC status on channel i), does not lead to a reset of the
OVRE flag (on channel i) as expected.
None
If a channel is disabled while a conversion is running and if a read of CDR is performed at the
same time as an end of conversion of any channel occurs, the EOC of the channel with the con-
version running may rise (whereas it has been disabled).
Do not take into account the EOC of a disabled channel
If “x” and “y” are two successively converted channels and “z” is yet another enabled channel
(“z” being neither “x” nor “y”), reading CDR on channel “z” at the same instant as an end of con-
version on channel “y” automatically clears EOC[x] instead of EOC[z].
1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun
2. GOVRE is inactive but DRDY is active, does correspond to a new general overrun con-
• EOC[x] already active,
• DRDY already active,
• GOVRE inactive,
• previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
condition but the GOVRE flag is not reset.
dition but the GOVRE flag is not set.
OVRE[x] rises as expected.
6175K–ATARM–30-Aug-10
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