AT91SAM7S64C-AU Atmel, AT91SAM7S64C-AU Datasheet - Page 723
AT91SAM7S64C-AU
Manufacturer Part Number
AT91SAM7S64C-AU
Description
IC ARM7 MCU 32BIT 64K 64LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7S16-MU.pdf
(779 pages)
Specifications of AT91SAM7S64C-AU
Package / Case
64-LQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
55MHz
Number Of I /o
32
Core Processor
ARM7
Program Memory Type
FLASH
Ram Size
16K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, SPI, SSC, UART/USART, USB
Core Size
16/32-Bit
Core
ARM7TDMI
Package
64LQFP
Device Core
ARM7TDMI
Family Name
AT91
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
32
Interface Type
SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
AT91SAM7S64B-AU::AT91SAM7S64B-AU
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
AT91SAM7S64C-AU
Manufacturer:
ATMEL
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Part Number:
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40.19.7.4
40.19.7.5
40.19.7.6
40.19.7.7
40.19.7.8
6175K–ATARM–30-Aug-10
SPI: LASTXFER (Last Transfer) behavior
SPI: SPCK Behavior in Master Mode
SPI: Chip Select and Fixed Mode
SPI: Baudrate Set to 1
SPI: Disable In Slave Mode
SPI: Disable Issue
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on
the data written in the SPI_TDR when the TX_EMPTY flag is set. If for example, the PDC writes
a “1” in the bit 24 (LASTXFER bit) of the SPI_TDR, the chip select will rise as soon as the
TXEMPTY flag is set.
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between
transfers.
SPCK pin can toggle out before the first transfer in Master Mode.
Problem Fix/Workaround
In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx
registers.
In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip
select 0, the output spi_size sampled by the PDC will depend on the field, BITS (Bits per Trans-
fer) of SPI_CSR0 register, whatever the selected Chip select is. For example, if SPI_CSR0 is
configured for a 10-bit transfer whereas SPI_CSR1 is configured for an 8-bit transfer, when a
transfer is performed in Fixed mode through the PDC, on Chip select 1, the transfer will be con-
sidered as a HalfWord transfer.
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the
BITS field of the SPI_CSR0 must be configured in 8 bits, in the same way as the BITS field of
the CSRy Register.
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency)
and when the BITS field of the SPI_CSR register (number of bits to be transmitted) equals an
ODD value (in this case 9,11,13 or 15), an additional pulse will be generated on output SPCK.
Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
None.
The SPI disable is not possible in slave mode.
Read first the received data, then perform the software reset.
The SPI Command “SPI Disable” is not possible during a transfer, it must be performed only
after TX_EMPTY rising else there is everlasting dummy transfers occur.
None.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM7S Series Preliminary
723
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