MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 316

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Fast Ethernet Controller (FEC)
Table 17-2
Table 17-3
17-6
IPSBAR Offset
•
•
0x10EC
0x10C4
0x10E4
0x10E8
0x111C
0x114C
0x1004
0x1008
0x1010
0x1014
0x1024
0x1040
0x1044
0x1064
0x1084
0x1118
0x1120
0x1124
0x1144
0x1150
0x1180
0x1184
0x1188
Control/status registers
Event/statistic counters held in the MIB block
defines the top level memory map.
shows the FEC register memory map.
Interrupt Event Register (EIR)
Interrupt Mask Register (EIMR)
Receive Descriptor Active Register (RDAR)
Transmit Descriptor Active Register (TDAR)
Ethernet Control Register (ECR)
MII Management Frame Register (MMFR)
MII Speed Control Register (MSCR)
MIB Control/Status Register (MIBC)
Receive Control Register (RCR)
Transmit Control Register (TCR)
Physical Address Low Register (PALR)
Physical Address High Register (PAUR)
Opcode/Pause Duration (OPD)
Descriptor Individual Upper Address Register (IAUR)
Descriptor Individual Lower Address Register (IALR)
Descriptor Group Upper Address Register (GAUR)
Descriptor Group Lower Address Register (GALR)
Transmit FIFO Watermark (TFWR)
FIFO Receive Bound Register (FRBR)
FIFO Receive FIFO Start Register (FRSR)
Pointer to Receive Descriptor Ring (ERDSR)
Pointer to Transmit Descriptor Ring (ETDSR)
Maximum Receive Buffer Size (EMRBR)
IPSBAR + 0x1000 – 11FF
IPSBAR + 0x1200 – 12FF
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Address
Table 17-3. FEC Register Memory Map
Register
Table 17-2. Module Memory Map
Control/Status Registers
MIB Block Counters
Width
Function
(bits)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0x05EE_0001
0xF000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0600
0x0000_0500
Reset Value
See Section
See Section
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Freescale Semiconductor
Section/Page
17.4.10/17-16
17.4.11/17-17
17.4.12/17-18
17.4.13/17-19
17.4.14/17-19
17.4.15/17-20
17.4.16/17-20
17.4.17/17-21
17.4.18/17-21
17.4.19/17-22
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17.4.3/17-10
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