MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 464

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

I
Various combinations of read/write formats are then possible:
24-10
2
C Interface
I2C_SCL
I2C_SDA
•
•
•
Example 1:
Example 2:
Example 3:
ST
Note: No acknowledge on the last byte
The first example in
The transfer direction is not changed.
The second example in
At the moment of the first acknowledge, the master-transmitter becomes a master-receiver and the
slave-receiver becomes slave-transmitter.
In the third example in
repeated START signal. This is to communicate with same slave in a different mode without
releasing the bus. The master transmits data to the slave first, and then the master reads data from
slave by reversing the R/W bit.
7-bit Slave
Address
START
Signal
ST = Start
SP = Stop
A = Acknowledge (
A = Not Acknowledge (
Rept ST = Repeated Start
ST
ST
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
1
7bit Slave Address
7bit Slave Address
2
Master Reads from Slave
R/W
1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Calling Address
I2C_
3
A
I2C_
Figure 24-11
SDA low)
4
Figure 24-11. Data Transfer, Combined Format
Figure 24-11
Figure
SDA high)
Data
5
R/W
R/W
6
Figure 24-10. Repeated START
24-11, START condition and slave address are repeated using the
0
1
lsb
7
is the case of master-transmitter transmitting to slave-receiver.
A
A
A
is the master reading the slave immediately after the first byte.
R/W
8
Rept
ST
ACK
Bit
9
Data
Data
XX
7-bit Slave
Address
Repeated
START
Signal
From Master to Slave
From Slave to Master
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
msb
A
1
A
A
R/W
0
2
A
New Calling Address
Data
Data
3
Master Writes to Slave
Data
4
A/A
5
A
SP
SP
6
A
Freescale Semiconductor
lsb
Data
7
R/W
8
A/A
ACK
No
9
Bit
SP
STOP
Signal