MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 390

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

General Purpose Timer Modules (GPTA and GPTB)
20.8.2
PAOVF is set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the PAOVI bit in
GPTPACTL is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to this flag.
20.8.3
PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets
PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the
PAI bit in GPTPACTL is also set, PAIF generates an interrupt request. Clear PAIF by writing a 1 to this
flag.
20.8.4
TOF is set when the GPT counter rolls over from 0xFFFF to 0x0000. If the GPTSCR2[TOI] bit is also set,
TOF generates an interrupt request. Clear TOF by writing a 1 to this flag.
20-22
Pulse Accumulator Overflow (PAOVF)
Pulse Accumulator Input (PAIF)
Timer Overflow (TOF)
When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input capture
read or an output compare write clears the corresponding channel flag.
When a channel flag is set, it does not inhibit subsequent output compares
or input captures
When the fast flag clear all enable bit, GPTSCR1[TFFCA], is set, any access
to the pulse accumulator counter registers clears all the flags in GPTPAFLG.
When the fast flag clear all enable bit, GPTSCR1[TFFCA], is set, any access
to the pulse accumulator counter registers clears all the flags in GPTPAFLG.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
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Freescale Semiconductor