71M6532D-IGTR/F Maxim Integrated Products, 71M6532D-IGTR/F Datasheet - Page 36
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
71M6532D-IGTR/F
Manufacturer Part Number
71M6532D-IGTR/F
Description
IC ENERGY METER 128KB 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6531D-IMRF.pdf
(120 pages)
Specifications of 71M6532D-IGTR/F
Mounting Style
SMD/SMT
Package / Case
LQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
71M6532D-IGTR/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
crystals are accurate and do not require a high-current oscillator circuit. The oscillator of the 71M6531D/F
and 71M6532D/F has been designed specifically to handle these crystals and is compatible with their
high impedance and limited power handling capability.
Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to Section
Real-Time Clock (RTC)
The oscillator is powered directly and only from VBAT, which therefore must be connected to a DC voltage
source. The oscillator requires approximately 100 nA, which is negligible compared to the internal leakage
of a battery.
The oscillator may appear to work when VBAT is not connected, but this mode of operation is not
recommended.
include:
•
•
•
•
•
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see Section
1.4.7 Timers and
scaled MCK output (making them multiples of 32768 Hz), and the clock skew is matched so that the rising
edges of CKADC, CKCE, CK32 and CKMPU are aligned.
Data Sheet 71M6531D/F-71M6532D/F
1.5
1.5.1
The oscillator of the 71M6531D/F and 71M6532D/F drives a standard 32.768 kHz watch crystal. These
1.5.2
Timing for the device is derived from the 32.768 kHz crystal oscillator output. On-chip timing functions
The master clock, MCK, is generated by an on-chip PLL that multiplies the oscillator output frequency
(CK32) by 2400 to provide approximately 80 MHz (78.6432 MHz). A divider controlled by the I/O RAM
bits M40MHZ and M26MHZ permits scaling of MCK by ½, ⅓ and ¼. All other clocks are derived from this
36
CKPLL
MCK
CKCE
CKADC / CKFIR
CKMPU maximum
CK32
**
***
†
The MPU clock (CKMPU)
The emulator clock (2 x CKMPU)
The clock for the CE (CKCE)
The clock driving the delta-sigma ADC along with the FIR (CKADC, CKFIR)
A real time clock (RTC).
CKCE = 9.8304 MHz when CE10MHZ is set, 4.9152 MHz otherwise.
Default state at power-up
The maximum CKMPU frequency. CKMPU can be reduced from this rate using MPU_DIV[2:0].
If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain
VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.
Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.
On-Chip Resources
Oscillator
Internal Clocks
Clock
Counters).
for more information.
Crystal
CKPLL
MCK
MCK
MCK
MCK
© 2005-2010 TERIDIAN Semiconductor Corporation
Derived
From
Table 37
Table 37: Clock System Summary
78.6432 MHz
39.3216 MHz
4.9152
MHz
4.9152 MHz
9.8304 MHz
32.768 kHz
provides a summary of the available clock functions.
†
÷2 / [1,0]
MCK Divider / [M40MHZ, M26MHZ]
9.8304
MHz
***
†
78.6432
MHz
26.2144
MHz
6.5536MHz
6.5536 MHz
6.5536 MHz
***
32.768 kHz
÷3 / [0,1]
78.6432
MHz
19.6608
MHz
4.9152 MHz
4.9152 MHz
4.9152 MHz
***
32.768 kHz
÷4
**
/ [0,0]
FDS 6531/6532 005
off
112 kHz
off
28 kHz
28 kHz
Brownout
Mode
1.5.3
v1.3