71M6532D-IGTR/F Maxim Integrated Products, 71M6532D-IGTR/F Datasheet - Page 89
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71M6532D-IGTR/F
Manufacturer Part Number
71M6532D-IGTR/F
Description
IC ENERGY METER 128KB 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6531D-IMRF.pdf
(120 pages)
Specifications of 71M6532D-IGTR/F
Mounting Style
SMD/SMT
Package / Case
LQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
71M6532D-IGTR/F
Manufacturer:
Maxim Integrated
Quantity:
10 000
•
•
•
When different CE codes are used, a different set of environment parameters needs to be established.
The exact values for these parameters are stated in the Application Notes and other documentation
accompanying the CE codes.
Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see
the product of the number of cycles per frame and the number of conversions per frame must be 12 (allowing
for one settling cycle).
During operation, CHOP_E[1:0] = 00 enables the automatic chopping mode and forces an alternate
multiplexer sequence at regular intervals. This enables accurate temperature measurement.
sag warning flags for VA and VB as well as F
FDS 6531/6532 005
•
4.3.5
4.3.6
The CESTATUS register provides information about the status of voltage and input AC signal frequency,
which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. It contains
frequency. CESTATUS represents the status flags for the preceding CE code pass (CE busy interrupt).
Sag alarms are not remembered from one code pass to the next. The CE Status word is refreshed at
every CE_BUSY interrupt. The significance of the bits in CESTATUS is shown in
required in the interrupt handler of the MPU. Rather than reading the CE status word at every CE_BUSY
interrupt and interpret the sag bits, it is recommended that the MPU activate the YPULSE output to generate
interrupts when a sag occurs (see the description of the CECONFIG register)
v1.3
Since the CE_BUSY interrupt typically occurs at 2520.6 Hz, it is desirable to minimize the computation
CE Address
EQU[2:0]
Select the values for SLOT0_SEL[3:0] = 0, SLOT1_SEL[3:0] = 1, SLOT2_SEL[3:0] = 2, SLOT3_SEL[3:0]
= 3
Select the values for SLOT0_ALTSEL[3:0] = 0x0A, SLOT1_ALTSEL[3:0] = 1, SLOT2_ALTSEL[3:0] =
0x0B, SLOT3_ALTSEL[3:0] = 3.
Set CHOP_E[1:0] = 00.
Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or a power failure detection interrupt.
0x80
0
1
2
CE Calculations
CE Status and Control
CE codes should only be used with environment parameters specified in this document or in the
applicable CE code description. Changing environment parameters at random will lead to unpre-
dictable results.
VA IA (1 element, 2W 1
with tamper detection
VA*(IA-IB)/2
(1 element, 3W 1
VA*IA + VB*IB
(2 element, 4W 2
Watt & VAR Formula
(WSUM/VARSUM)
Table 56: CE EQU[2:0] Equations and Element Input Mapping
CESTATUS
Name
© 2005-2010 TERIDIAN Semiconductor Corporation
φ
φ
)
)
See description of CESTATUS bits in
φ
)
VA*(IA-IB)/2
VAR0SUM
0
W0SUM/
, the derived clock operating at the fundamental input
VA*IA
VA*IA
(VA * IB)/2
VAR1SUM
Element Input Mapping
W1SUM/
VA*IB
VB*IB
Description
Data Sheet 71M6531D/F-71M6532D/F
Table
Figure
I0SQSUM
IA-IB
57.
Table
IA
IA
19). This means that
57.
I1SQSUM
IB
IB
IB
89