CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 562
CSM9S12XDT512SLK
Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of CSM9S12XDT512SLK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.3.2.5
The VREGAPIRH and VREGAPIRL register allows the configuration of the VREG_3V3 autonomous
periodical interrupt rate.
562
APIR[11:0]
Reset
Reset
Field
11-0
W
W
R
R
APIR7
Autonomous Periodical Interrupt Rate Bits — These bits define the timeout period of the API. See
for details of the effect of the autonomous periodical interrupt rate bits. Writable only if APIFE = 0 of VREGAPICL
register.
Figure 14-6. Autonomous Periodical Interrupt Rate High Register (VREGAPIRH)
Autonomous Periodical Interrupt Rate High and Low Register
(VREGAPIRH / VREGAPIRL)
Figure 14-7. Autonomous Periodical Interrupt Rate Low Register (VREGAPIRL)
0
0
0
7
7
= Unimplemented or Reserved
APIR6
Table 14-7. VREGAPIRH / VREGAPIRL Field Descriptions
0
0
0
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
APIR5
0
0
0
5
5
APIR4
0
0
0
4
4
Description
APIR11
APIR3
0
0
3
3
APIR10
APIR2
0
0
2
2
Freescale Semiconductor
APIR9
APIR1
0
0
1
1
Table 14-8
APIR8
APIR0
0
0
0
0
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