CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 876

• Manufacturer Part Number: CSM9S12XDT512SLK
• Description: KIT STUDENT LEARNING 16BIT
• Manufacturer: Freescale Semiconductor

Specifications of CSM9S12XDT512SLK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.69 Port AD1 Data Direction Register 1 (DDR1AD1)
Read: Anytime.
Write: Anytime.
This register configures pins PAD[15:08] as either input or output.
878
DDR1AD1[15:8]
Reset
Field
W
R
7–0
DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19
0
7
Data Direction Port AD1 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
Note: To use the digital input function on port AD1 the ATD1 digital input enable register (ATD1DIEN1) has
read on PTAD11 register, when changing the DDR1AD1 register.
to be set to logic level “1”.
Figure 22-71. Port AD1 Data Direction Register 1 (DDR1AD1)
0
6
Table 22-62. DDR1AD1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
0
4
Description
0
3
0
2
Freescale Semiconductor
0
1
DDR1AD18
0
0