CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 753

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CSM9S12XDT512SLK

Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM9S12XDT512SLK

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
20.3.2.4
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Freescale Semiconductor
Address: 0x0023
CDCM[1:0]
ABCM[1:0]
Reset
Field
3–2
1–0
W
R
CDCM
ABCM
00
01
10
11
00
01
10
11
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
described in
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in
Debug Control Register2 (DBGC2)
0
0
7
= Unimplemented or Reserved
Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
Table
Table
0
0
6
20-14.
20-15.
Match 0 mapped to comparator A/B outside range....... Match1 disabled.
Match2 mapped to comparator C/D outside range....... Match3 disabled.
Match 0 mapped to comparator A/B inside range....... Match1 disabled.
Match2 mapped to comparator C/D inside range....... Match3 disabled.
Figure 20-6. Debug Control Register2 (DBGC2)
Table 20-13. DBGC2 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
Table 20-14. CDCM Encoding
Table 20-15. ABCM Encoding
0
0
4
Description
Description
Description
Reserved
Reserved
0
3
CDCM
Chapter 20 S12X Debug (S12XDBGV3) Module
0
2
0
1
ABCM
0
0
755

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