CSM9S12XDT512SLK Freescale Semiconductor, CSM9S12XDT512SLK Datasheet - Page 58
CSM9S12XDT512SLK
Manufacturer Part Number
CSM9S12XDT512SLK
Description
KIT STUDENT LEARNING 16BIT
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of CSM9S12XDT512SLK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 1 Device Overview MC9S12XD-Family
The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check
is ongoing. This is the case for:
The selected oscillator configuration is frozen with the rising edge of reset.
The pin can be configured to drive the internal system clock ECLKX2.
1.2.3.17
PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a
58
•
•
•
Power on reset or low-voltage reset
Clock monitor reset
Any reset while in self-clock mode or full stop mode
PE6 / MODB / TAGHI — Port E I/O Pin 6
Figure 1-11. Loop Controlled Pierce Oscillator Connections (PE7 = 1)
Figure 1-12. Full Swing Pierce Oscillator Connections (PE7 = 0)
MCU
EXTAL
Figure 1-13. External Clock Connections (PE7 = 0)
XTAL
MCU
MCU
EXTAL
EXTAL
MC9S12XDP512 Data Sheet, Rev. 2.21
XTAL
XTAL
R
S
R
B
Not Connected
Ceramic Resonator
Crystal or
CMOS-Compatible
External Oscillator
C
C
Ceramic Resonator
1
2
Crystal or
C
C
1
2
V
SSPLL
V
SSPLL
Freescale Semiconductor
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