HSP50216KIZ Intersil, HSP50216KIZ Datasheet - Page 11

• Manufacturer Part Number: HSP50216KIZ
• Description: IC DOWNCONVERTER DGTL 4CH 196BGA
• Manufacturer: Intersil

Specifications of HSP50216KIZ

• Function: Downconverter
• Rf Type: W-CDMA
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Backend Data Routing
A CIC filter has a gain of R
and N is the number of stages. Because the CIC filter gain
can become very large with decimation, an attenuator is
provided ahead of the CIC to prevent overflow. The 24 bits of
sample data are placed on the low 24 bits of a 69 bit bus
(width of the first CIC integrator) for a gain of 2
barrel shifter then provides a gain of 2
before passing the data onto the CIC. The overall gain in the
pre-CIC attenuator can therefore be programmed to be any
one of 32 values from 2
bits 18:14). This shift factor is adjusted to keep the total
barrel shifter and CIC filter between 0.5 and 1.0. The
equation which should be used to compute the necessary
shift factor is:
Shift Factor = 45 - Ceiling(log
NOTE: With a CIC order of zero, the CIC shifter does not have
sufficient range to route more than 10 bits to the back end since the
maximum gain is 2
28 27
DESTINATION BIT MAP
(BITS 28:18 OF FIR INSTRUCTIONS BIT FIELD)
28
27
26, 25
24
23
22:18
26
25 24 23 22 21 20 19 18
FILTER PROCESSOR SEQUENCE STEP NUMBER
AGC LOOP GAIN SELECT (PATH 01 ONLY)
UPDATE AGC LOOP (PATH 01 ONLY)
PATH 00 - - IMMEDIATE FILTER PROCESSOR FEEDBACK PATH
STROBE OUTPUT SECTION (START SERIAL OUTPUT WITH THIS SAMPLE)
FEED MAG/PHASE BACK TO FILTER PROCESSOR
-14
FROM
01 - - FIFO/AGC PATH
10 - - DIRECT OUT/CASCADE PATH
11 - - BOTH 00 AND 10 PATHS (FOR TEST)
(the least significant 14 bits are lost).
CIC
-45
N
, where R is the decimation factor
to 2
11
2
(R
-14
N
, inclusive (see IWA=*004,
)).
M
U
X
(4:0)
0
to 2
PATH 0
COMPUTE
31
ENGINE
FILTER
inclusive
-45
. A 32 bit
PATH 1
HSP50216
PATH 2
TIMER
FIFO/
Back End Section
One back-end processing section is provided per channel.
Each back end section consists of a filter compute engine, a
FIFO/timer for evenly spacing samples (important when
implementing interpolation filters and resamplers), an AGC
and a cartesian-to-polar coordinate conversion block. A
block diagram showing the major functional blocks and data
routing is shown above. The data input to the back end
section is through the filter compute engine. There are two
other inputs to the filter compute engine, they are a data
recirculation path for cascading filters and a magnitude and
dφ/dt feedback path for AM and FM filtering. There are seven
outputs from each back end processing section. These are I
and Q directly out of the filter compute engine (I2, Q2), I and
Q passed through the FIFO and AGC multipliers (I1, Q1),
magnitude (MAG), phase (or dφ/dt), and the AGC gain
control value (GAIN). The I2/Q2 outputs are used when
cascading back end stages. The routing of signals within the
back end processing section is controlled by the filter
compute engine. The routing information is embedded in the
instruction bit fields used to define the digital filter being
implemented in the filter compute engine.
FILTER
LOOP
AGC
MULT
MUX
AGC
EXT AGC
GAIN
POLAR
CART
TO
SHIFT
MAG: I
d/dt
x1, x2
x4, x8
M
U
X
dphi/dt: Q
August 17, 2007
I1
Q1
GAIN
I2
Q2
FN4557.6
PHASE
MAG