T5760-TGQ Atmel, T5760-TGQ Datasheet - Page 12

• Manufacturer Part Number: T5760-TGQ
• Description: IC RX 868MHZ ISM ASK/FSK 20-SOIC
• Manufacturer: Atmel

Specifications of T5760-TGQ

• Frequency: 868MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose Data Transmission Systems
• Current - Receiving: 7.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: T5760-TGQTR

Figure 11. Timing Diagram During Bit Check
Figure 12. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Figure 13. Timing Diagram for Failed Bit Check (Condition: CV_Lim >= Lim_max)
12
( Lim_min = 14, Lim_max = 24 )
IC_ACTIVE
Bit check
Dem_out
Bit-check-
counter
( Lim_min = 14, Lim_max = 24 )
IC_ACTIVE
Bit check
Dem_out
Bit-check-
counter
( Lim_min = 14, Lim_max = 24 )
IC_ACTIVE
Bit check
Dem_out
Bit-check-
counter
T5760/T5761
Start-up mode
Start-up mode
Start-up mode
T
T
T
Start-up
Start-up
Start-up
0
0
0
Figure 14, Figure 15 and Figure 16 illustrate the bit check for the bit-check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits
are enabled during T
fined during that period. When the bit check becomes active, the bit-check counter is
clocked with the cycle T
Figure 14 shows how the bit check proceeds if the bit-check counter value CV_Lim is
within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
Figure 15 the bit check fails as the value CV_Lim is lower than the limit Lim_min. The bit
check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 16.
1
1
1
2 3 4 5 6
2 3 4 5 6
2 3 4 5 6
T
1
7
7 8 1
XClk
Bit-check mode
2
1
2
3
T
Bit-check
2
4 5
3
3
4 5
Bit-check mode
1/2 Bit
4 5
6 7 8 9
Startup
T
6 7 8 9
Bit-check
6 7 8 9
XClk
Bit check failed ( CV_Lim < Lim_min )
. The output of the ASK/FSK demodulator (Dem_out) is unde-
1/2 Bit
10
.
11 12
10
1/2 Bit
10
11 12
Bit-check mode
11 12 13 14
13 14 15 16 17 18 19
T
Bit-check
15 16 17 18 1 2 3 4 5 6
Bit check ok
Sleep mode
0
T
Bit check failed ( CV_Lim >= Lim_max )
Sleep
20
21 22 23 24
1/2 Bit
7 8 9 10 11 12 13 14 15 1 2 3 4
Sleep mode
T
0
Sleep
Bit check ok
1/2 Bit
4561B–RKE–10/02