T5760-TGQ Atmel, T5760-TGQ Datasheet - Page 14

• Manufacturer Part Number: T5760-TGQ
• Description: IC RX 868MHZ ISM ASK/FSK 20-SOIC
• Manufacturer: Atmel

Specifications of T5760-TGQ

• Frequency: 868MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose Data Transmission Systems
• Current - Receiving: 7.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: T5760-TGQTR

Figure 15. Debouncing of the Demodulator Output
Figure 16. Steady L State Limited DATA Output Pattern After Transmission
Switching the Receiver
Back to Sleep Mode
14
Dem_out
Data_out (DATA)
IC_ACTIVE
Bit check
Dem_out
Data_out (DATA)
T5760/T5761
Start-up mode
t
DATA_min
After the end of a data transmission, the receiver remains active. Depending of the bit
Noise_Disable in the OPMODE register, the output signal at Pin DATA is high or
random noise pulses appear at Pin DATA (see chapter ’Digital Noise Suppression’). The
edge-to-edge time period t
higher than T
The receiver can be set back to polling mode via Pin DATA or via Pin POLLING/_ON.
When using Pin DATA, this pin must be pulled to Low for the period t1 by the connected
microcontroller. Figure 17 illustrates the timing of the OFF command (see Figure 32).
The minimum value of t1 depends on BR_Range. The maximum value for t1 is not
limited but it is recommended not to exceed the specified value to prevent erasing the
reset marker. Note also that an internal reset for the OPMODE and the LIMIT register
will be generated if t1 exceeds the specified values. This item is explained in more detail
in the chapter ‘Configuration of the Receiver’. Setting the receiver to sleep mode via
DATA is achieved by programming bit 1 to be ‘1’ during the register configuration. Only
one sync pulse (t3) is issued.
The duration of the OFF command is determined by the sum of t1, t2 and t10. After the
OFF command the sleep time T
is limited (see chapter ’Data Interface’).
t
ee
Bit-check mode
DATA_min
.
t
DATA_min
ee
of the majority of these noise pulses is equal or slightly
Sleep
Receiving mode
t
ee
elapses. Note that the capacitive load at Pin DATA
t
DATA_min
t
DATA_min
t
DATA_L_max
t
ee
4561B–RKE–10/02