T5760-TGQ Atmel, T5760-TGQ Datasheet - Page 13

• Manufacturer Part Number: T5760-TGQ
• Description: IC RX 868MHZ ISM ASK/FSK 20-SOIC
• Manufacturer: Atmel

Specifications of T5760-TGQ

• Frequency: 868MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: General Purpose Data Transmission Systems
• Current - Receiving: 7.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: T5760-TGQTR

Duration of the Bit Check
Receiving Mode
Digital Signal Processing
Figure 14. Synchronization of the Demodulator Output
4561B–RKE–10/02
Clock bit-check
counter
Dem_out
Data_out (DATA)
T
XClk
If no transmitter signal is present during the bit check, the output of the ASK/FSK
demodulator delivers random signals. The bit check is a statistical process and T
varies for each check. Therefore, an average value for T
characteristics. T
baud-rate range causes a lower value for T
tion in polling mode.
In the presence of a valid transmitter signal, T
that signal, f
thereby results in a longer period for T
pre-burst T
If the bit check was successful for all bits specified by N
receiving mode. According to Figure 9, the internal data signal is switched to Pin
DATA in that case and the data clock is available after the start bit has been detected
(see Figure 20). A connected microcontroller can be woken up by the negative edge at
Pin DATA or by the data clock at Pin DATA_CLK. The receiver stays in that condition
until it is switched back to polling mode explicitly.
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different
ways and as a result converted into the output signal data. This processing depends on
the selected baud-rate range (BR_Range). Figure 14 illustrates how Dem_out is syn-
chronized by the extended clock cycle T
counter. Data can change its state only after T
period t
The minimum time period between two edges of the data signal is limited to
t
same time it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller.
The maximum time period for DATA to stay Low is limited to T
employed to ensure a finite response time in programming or switching off the receiver
via Pin DATA. T
the transmitter data stream. Figure 16 gives an example where Dem_out remains Low
after the receiver has switched to receiving mode.
ee
³ T
DATA_min
ee
of the Data signal as a result is always an integral multiple of T
Preburst
Sig
. This implies an efficient suppression of spikes at the DATA output. At the
, and the count of the checked bits, N
DATA_L_max
.
Bit-check
t
ee
depends on the selected baud-rate range and on T
is thereby longer than the maximum time period indicated by
Bit-check
XClk
Bit-check
. This clock is also used for the bit-check
requiring a higher value for the transmitter
Bit-check
XClk
resulting in a lower current consump-
has elapsed. The edge-to-edge time
Bit-check
is dependent on the frequency of
Bit-check
Bit-check
. A higher value for N
DATA_L_max
, the receiver switches to
T5760/T5761
is given in the electrical
. This function is
XClk
Clk
.
. A higher
Bit-check
Bit-check
13