AT86RF212-ZU Atmel, AT86RF212-ZU Datasheet - Page 76

• Manufacturer Part Number: AT86RF212-ZU
• Description: IC TXRX ZIGBE/802.15.4/ISM 32QFN
• Manufacturer: Atmel

Specifications of AT86RF212-ZU

• Frequency: 700MHz, 800MHz, 900MHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, ISM
• Applications: ISM, ZigBee™
• Power - Output: 10dBm
• Sensitivity: -110dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 9.2mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 769 MHz to 935 MHz
• Interface Type: SPI
• Noise Figure: 7 dB
• Output Power: 21 dB
• Operating Supply Voltage: 1.8 V, 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

76
AT86RF212
Table 6-16. Register 0x28 (IEEE_ADDR_4)
Register 0x29 (IEEE_ADDR_5):
This register contains bits [47:40] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-17. Register 0x29 (IEEE_ADDR_5)
Register 0x2A (IEEE_ADDR_6):
This register contains bits [55:48] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-18. Register 0x2A (IEEE_ADDR_6)
Register 0x2B (IEEE_ADDR_7):
This register contains bits [63:56] of the 64-bit IEEE extended address for Frame Filter
address recognition.
Table 6-19. Register 0x2B (IEEE_ADDR_7)
Register 0x2E (CSMA_SEED_1):
The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of
the CSMA seed for the CSMA-CA algorithm, as well as control bits for the Frame Filter
and RX_AACK transaction.
Table 6-20. Register 0x2E (CSMA_SEED_1)
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
7
AACK_FVN_MODE
R/W
0
7
0
7
0
7
0
7
0
6
0
6
0
6
0
6
0
6
AACK_FVN_MODE
R/W
1
5
0
5
0
5
0
5
0
4
0
4
0
4
0
4
0
IEEE_ADDR_4[7:0]
IEEE_ADDR_5[7:0]
IEEE_ADDR_6[7:0]
IEEE_ADDR_7[7:0]
R/W
R/W
R/W
R/W
5
AACK_SET_PD
R/W
0
3
0
3
0
3
0
3
0
2
0
2
0
2
0
2
0
8168C-MCU Wireless-02/10
4
AACK_DIS_ACK
R/W
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0