EM250-RTR Ember, EM250-RTR Datasheet - Page 63

• Manufacturer Part Number: EM250-RTR
• Description: IC ZIGBEE SYSTEM-ON-CHIP 48-QFN
• Manufacturer: Ember
• Series: EM250r

Specifications of EM250-RTR

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: Home/Building Automation, Industrial Control and Monitoring
• Power - Output: 3dBm
• Sensitivity: -97dBm
• Voltage - Supply: 2 V ~ 3.6 V
• Current - Receiving: 35.5mA
• Current - Transmitting: 33mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 5kB SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• For Use With: 636-1009 - PROGRAMMER USB FLASH EM250/260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate - Maximum: -
• Other names: 636-1000-2

indication: setting the appropriate
priate DMA buffer after it has unloaded.
Receiving a character always requires transmitting a character. In a case when a long stream of receive char-
acters is expected, a long sequence of (dummy) transmit characters must be generated. To avoid software or
transmit DMA initiating these transfers (and consuming unnecessary bandwidth), the SPI serializer can be in-
structed to retransmit the last transmitted character or to transmit a busy token (
by the register bit
when the transmit FIFO is empty and the transmit serializer is idle, as indicated by a cleared
register bit in the
Every time an automatic character transmission is started, a transmit underrun is detected (as there is no data
in transmit FIFO) and the register bit
abling the automatic character transmission, the reception of new characters stops and the receive FIFO holds
characters just received.
Note: The event Receive DMA complete does not automatically mean receive FIFO empty.
Interrupts are generated by one of the following events:
To generate interrupts to the CPU, the interrupt masks in the
abled.
5.3.1.2
The SC2 SPI Slave controller is enabled with the
The SC2 SPI Slave controller receives its clock from an external SPI master device and supports rates up to
5Mbps.
The SC2 SPI Slave supports various frame formats depending upon the clock polarity (
(
and
Note: Switching the SPI configuration from
SC_SPIPHA
SC_SPIORD
Transmit FIFO empty and last character shifted out (0 to 1 transition of
Transmit FIFO changed from full to not full (0 to 1 transition of
Receive FIFO changed from empty to not empty (0 to 1 transition of
Transmit DMA buffer A/B complete (1 to 0 transition of
Receive DMA buffer A/B complete (1 to 0 transition of
Received and lost character while receive FIFO was full (Receive overrun error)
Transmitted character while transmit FIFO was empty (Transmit underrun error)
SC2_MODE=0
before the first intended byte.
SPI Slave Mode
), and direction of data (
are defined within the
SC2_SPISTAT
SC_SPIRPT
and reinitializing the SPI will cause an extra byte (
in the
register.
SC_TX/RXDMARST
SC_SPIORD
SC2_SPICFG
INT_SCTXUND
SC2_SPICFG
SC_SPIPOL=1
SC_SPIMST
) (see Table 25). The register bits
register. This functionality can only be enabled (or disabled)
in the
registers.
bit in the
INT_SC2FLAG
SC_RXACTA/B
to
SC_TXACTA/B
cleared in the
INT_SC2CFG
SC_SPIPOL=0
SC2_DMACTRL
SC_SPITXFREE
0xFE
)
SC_SPIRXVAL
register is set. Note that after dis-
)
SC2_SPICFG
and
SC_SPITXIDLE
without subsequently setting
) to be transmitted immediately
register, or loading the appro-
INT_CFG
0xFF
SC_SPIPOL
)
SC_SPIPOL
)
), which is determined
register.
register must be en-
120-0082-000I
)
SC_SPITXIDLE
,
SC_SPIPHA
), clock phase
EM250
,
63