MC33696FCAE Freescale Semiconductor, MC33696FCAE Datasheet - Page 28

• Manufacturer Part Number: MC33696FCAE
• Description: IC UHF RECEIVER PLL TUNED 32-QFN
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC33696FCAE

• Frequency: 304, 315, 426, 434, 868 & 915MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Data Transfer
• Power - Output: 7.5dBm
• Sensitivity: -106dBm
• Voltage - Supply: 2.7 V ~ 3.3 V, 4.5 V ~ 5.5 V
• Current - Receiving: 10.3mA
• Current - Transmitting: 13mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): -20C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Modulation Type: FSK/OOK
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Configuration Mode
Bits N[1:0] specify the number of accessed registers, as defined in
Bits A[4:0] specify the address of the first register to access. This address is then incremented internally
by N after each data byte transfer.
R/W specifies the type of operation:
Thus, this bit is associated with the presence of information on MOSI (when writing) or MISO (when
reading).
Figure 20
a slave. A received byte is considered internally on the eighth falling edge of SCLK. Consequently, the last
received bits, which do not form a complete byte, are lost.
Refer to
If several SPI accesses are done, a high and low level is applied to CONFB, and so on. By applying a high
level to STROBE, the MC33696 never enters standby mode. If there is no way to configure the level on
STROBE, the time interval between two SPI accesses must be less than one digital clock period T
28
Bit Name
0 = Read
1 = Write
Section 21.9, “Digital Interface
and
Figure 21
A low level applied to CONFB and a high level to STROBE do not affect
the configuration register contents.
See
the SEB pin.
Section 10, “MCU
Bit 7
N1
show write and read operations in a typical SPI transfer. In both cases, the SPI is
Bit 6
N0
N[1:0]
Table 7. Number N of Accessed Registers
00
01
10
11
Interface,” for more details about setting the level on
Figure 19. Command Byte
MC33696 Data Sheet, Rev. 12
Bit 5
Timing,” to view the timing definition for SPI communication.
A4
Number N of Accessed Registers
NOTE
Bit 4
A3
1
2
4
8
Bit 3
A2
Table
Bit 2
A1
7.
Bit 1
A0
Freescale Semiconductor
Bit 0
R/W
digclk
.