MC33696FCAE Freescale Semiconductor, MC33696FCAE Datasheet - Page 38

• Manufacturer Part Number: MC33696FCAE
• Description: IC UHF RECEIVER PLL TUNED 32-QFN
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC33696FCAE

• Frequency: 304, 315, 426, 434, 868 & 915MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Data Transfer
• Power - Output: 7.5dBm
• Sensitivity: -106dBm
• Voltage - Supply: 2.7 V ~ 3.3 V, 4.5 V ~ 5.5 V
• Current - Receiving: 10.3mA
• Current - Transmitting: 13mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): -20C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Modulation Type: FSK/OOK
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Description
If the data manager is disabled, the incoming signal data rate must be lower than or equal to the data
manager maximum data rate.
TRXE (Transceiver Enable) enables the whole transceiver. This bit must be set to high level if MCU wakes
the MC33696 to enter receive or transmit mode.
DME (Data Manager Enable) enables the data manager.
SOE (Strobe Oscillator Enable) enables the strobe oscillator.
Figure 27
OLS (Out of Lock Status) indicates the current status of the PLL.
LVDS (Low Voltage Detection Status) indicates that a low voltage event has occurred when LVDE = 1.
This bit is read-only and is cleared after a read access.
ILA[1:0] (Input Level Attenuation) define the RF input level attenuation.
38
Reset Value
Bit Name
•
•
•
Access
Low-pass data filter
Low-pass average filter generating the data slicer reference, if DSREF is set
Data manager
0 = standby mode
1 = other modes can be activated
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = The PLL is in lock-in range
1 = The PLL is out of lock-in range
0 = No low voltage detected
1 = Low voltage detected
describes configuration register 3, CONFIG3.
DR1
0
0
1
1
AFF1
Bit 7
R/W
DR0
0
0
1
0
1
AFF0
Cut-off Frequency
Bit 6
R/W
0
Table 10. Base Band Parameter Configuration
Data Filter
12 kHz
24 kHz
48 kHz
6 kHz
Bit 5
OLS
Figure 27. CONFIG3 Register
R
1
MC33696 Data Sheet, Rev. 12
LVDS
Bit 4
R
1
Cut-off Frequency
Average Filter
0.5 kHz
1 kHz
2 kHz
4 kHz
Bit 3
ILA1
R/W
0
Bit 2
ILA0
R/W
0
Data Rate Range
Data Manager
16–22.4 kBd
8–10.6 kBd
OLA1
2–2.8 kBd
4–5.6 kBd
Bit 1
R/W
0
Freescale Semiconductor
OLA0
Bit 0
R/W
0
Addr
$02