MC33696FCAE Freescale Semiconductor, MC33696FCAE Datasheet - Page 7

• Manufacturer Part Number: MC33696FCAE
• Description: IC UHF RECEIVER PLL TUNED 32-QFN
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC33696FCAE

• Frequency: 304, 315, 426, 434, 868 & 915MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: FSK, OOK
• Applications: General Data Transfer
• Power - Output: 7.5dBm
• Sensitivity: -106dBm
• Voltage - Supply: 2.7 V ~ 3.3 V, 4.5 V ~ 5.5 V
• Current - Receiving: 10.3mA
• Current - Transmitting: 13mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-QFN
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Operating Temperature (min): -20C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Modulation Type: FSK/OOK
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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The receiver is based on a superheterodyne architecture with an intermediate frequency IF (see
Its input is connected to the RFIN pin. Frequency down conversion is done by a high-side injection I/Q
mixer driven by the frequency synthesizer. An integrated poly-phase filter performs rejection of the image
frequency.
The low intermediate frequency allows integration of the IF filter providing the selectivity. The IF Filter
center frequency is tuned by automatic frequency control (AFC) referenced to the crystal oscillator
frequency.
Sensitivity is met by an overall amplification of approximately 96 dB, distributed over the reception chain,
comprising low-noise amplifier (LNA), mixer, post-mixer amplifier, and IF amplifier. Automatic gain
control (AGC), on the LNA and the IF amplifier, maintains linearity and prevents internal saturation.
Sensitivity can be reduced using four programmable steps on the LNA gain.
Amplitude demodulation is achieved by peak detection. Frequency demodulation is achieved in two steps:
the IF amplifier AGC is disabled and acts as an amplitude limiter; a filter performs a frequency-to-voltage
conversion. The resulting signal is then amplitude demodulated in the same way as in the case of amplitude
modulation with an adaptive voltage reference.
A low-pass filter improves the signal-to-noise ratio of demodulated data. A data slicer compares
demodulated data with a fixed or adaptive voltage reference and provides digital level data.
This digital data is available if the integrated data manager is not used.
If used, the data manager performs clock recovery and decoding of Manchester coded data. Data and clock
are then available on the serial peripheral interface (SPI). The configuration sets the data rate range
managed by the data manager and the bandwidth of the low-pass filter.
An internal low-frequency oscillator can be used as a strobe oscillator to perform an automatic wakeup
sequence.
It is also possible to define two different configurations for the receiver (frequency, data rate, data manager,
modulation, etc.) that are automatically loaded during wakeup or under MCU control.
If the PLL goes out of lock, received data is ignored.
Freescale Semiconductor
Receiver Functional Description
If LVDE = 1, the LVD module remains enabled. The circuit cannot be put
in standby mode, but remains in LVD mode with a higher quiescent current,
due to the monitoring circuitry. LVD function is not accurate in standby
mode.
MC33696 Data Sheet, Rev. 12
NOTE
Receiver Functional Description
Figure
1).
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