AT86RF231-ZFR Atmel, AT86RF231-ZFR Datasheet - Page 10

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AT86RF231-ZFR

Manufacturer Part Number
AT86RF231-ZFR
Description
TXRX LOW POWER 2.4GHZ 32VQFN
Manufacturer
Atmel
Datasheet

Specifications of AT86RF231-ZFR

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Applications
Industrial Monitoring and Control, Wireless Alarm and Security Systems
Power - Output
-17dBm ~ 3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.3mA
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
2405 MHz to 2480 MHz
Interface Type
SPI
Noise Figure
6 dB
Output Power
20 dB
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
12.3 mA
Minimum Operating Temperature
- 40 C
Modulation
OQPSK
Protocol Supported
802.15.4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
AT86RF231-ZFR
AT86RF231-ZFRTR
4. General Circuit Description
Figure 4-1.
8111C–MCU Wireless–09/09
DIG3/4
RFP
RFN
DIG1/2
Analog Domain
AT86RF231 Block Diagram
LNA
AD
PA
This single-chip radio transceiver provides a complete radio transceiver interface between an
antenna and a microcontroller. It comprises the analog radio, digital modulation and demodula-
tion including time and frequency synchronization and data buffering. The number of external
components is minimized such that only the antenna, the crystal and decoupling capacitors are
required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and
reception, thus no external antenna switch is needed.
The AT86RF231 block diagram is shown in
The received RF signal at pins RFN and RFP is differentially fed through the low-noise amplifier
(LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter
(BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital
converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled by the
digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-
length block coding (spreading) according to
the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL), to
ensure the coherent phase modulation required for demodulation of O-QPSK signals. The fre-
quency-modulated signal is fed to the power amplifier (PA).
A differential pin pair DIG3/DIG4 can be enabled to control an external RF front-end.
Two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and digital 1.8V
supply.
PPF
ext. PA and Power
Control
Antenna Diversity
PLL
BPF
XOSC
Limiter
AGC
FTN, BATMON
AVREG
TX Data
ADC
RSSI
Figure 4-1 on page
[1]
and [2]. The modulation signal is generated in
Digital Domain
RX BBP
TX BBP
Frame
Buffer
Configuration Registers
Control Logic
DVREG
10.
AES
(Slave)
AT86RF231
SPI
/SEL
MISO
MOSI
SCLK
IRQ
CLKM
DIG2
/RST
SLP_TR
10

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