AT86RF231-ZFR Atmel, AT86RF231-ZFR Datasheet - Page 19

• Manufacturer Part Number: AT86RF231-ZFR
• Description: TXRX LOW POWER 2.4GHZ 32VQFN
• Manufacturer: Atmel

Specifications of AT86RF231-ZFR

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Applications: Industrial Monitoring and Control, Wireless Alarm and Security Systems
• Power - Output: -17dBm ~ 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.3mA
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2405 MHz to 2480 MHz
• Interface Type: SPI
• Noise Figure: 6 dB
• Output Power: 20 dB
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 12.3 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: AT86RF231-ZFR; AT86RF231-ZFRTR

6.2
Table 6-2.
6.2.1
8111C–MCU Wireless–09/09
Bit 7
1
1
0
0
0
0
SPI Protocol
Register Access Mode
Bit 6
0
1
0
1
0
1
SPI Command Byte definition
Bit 5
1
1
0
0
Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see
Table 6-2 on page
additional mode-dependent information.
Each SPI transfer returns bytes back to the SPI master on MISO. The content of the first byte
(see value "PHY_STATUS" in
after reset. To transfer status information of the radio transceiver to the microcontroller, the con-
tent of the first byte can be configured with register bits SPI_CMD_MODE (register 0x04,
TRX_CTRL_1). For details, refer to
24.
In
stated with XX on MOSI are ignored by the radio transceiver, but need to have a valid logic level.
Return values on MISO stated as XX shall be ignored by the microcontroller.
The different access modes are described within the following sections.
A register access mode is a two-byte read/write operation initiated by /SEL = L. The first trans-
ferred byte on MOSI is the command byte including an identifier bit (bit7 = 1), a read/write select
bit (bit 6), and a 6-bit register address.
On read access, the content of the selected register address is returned in the second byte on
MISO (see
Figure 6-4.
Note:
On write access, the second byte transferred on MOSI contains the write data to the selected
address (see
Bit 4
Figure 6-4 on page 19
Register address [5:0]
Register address [5:0]
1. Each SPI access can be configured to return radio controller status information
Bit 3
Figure 6-4 on page
(PHY_STATUS) on MISO, for details refer to
tion” on page
MOSI
MISO
Figure 6-5 on page
Packet Structure - Register Read Access
Reserved
Reserved
Reserved
Reserved
Bit 2
19) with MSB first. This command byte defines the SPI access mode and
1
24.
Bit 1
byte 1 (command byte)
0
to
PHY_STATUS
Figure 6-14 on page 23
Figure 6-4 on page 19
19).
ADDRESS[5:0]
Bit 0
20).
Section 6.3.1 “Register Description - SPI Control” on page
Access Mode
Register access
Frame Buffer access
SRAM access
(1)
Section 6.3 “Radio Transceiver Status informa-
to
and the following chapters logic values
Figure 6-14 on page
READ DATA[7:0]
byte 2 (data byte)
XX
Access Type
Read access
Write access
Read access
Write access
Read access
Write access
AT86RF231
23) is set to zero
19