AT86RF231-ZU Atmel, AT86RF231-ZU Datasheet - Page 143

• Manufacturer Part Number: AT86RF231-ZU
• Description: IC TXRX ZIGBE/802.15.4/ISM 32QFN
• Manufacturer: Atmel

Specifications of AT86RF231-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Applications: Industrial Monitoring and Control, Wireless Alarm and Security Systems
• Power - Output: -17dBm ~ 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.3mA
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2405 MHz to 2480 MHz
• Interface Type: SPI
• Noise Figure: 6 dB
• Output Power: 20 dB
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 12.3 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Transmitting Current: 11.6mA
• Data Rate: 2Mbps
• Frequency Range: 2.405GHz To 2.48GHz
• Modulation Type: O-QPSK
• Sensitivity Dbm: -101dBm
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.4.3
11.4.4
8111C–MCU Wireless–09/09
Bit
+0x0A
Read/Write
Reset Value
Antenna Diversity Sensitivity Control
Register Description
R/W
7
1
Generally, the Antenna Diversity algorithm is enabled with register bit ANT_DIV_EN (register
0x0D, ANT_DIV) set. In this case the control of an antenna diversity switch must be enabled by
register bit ANT_EXT_SW_EN (register 0x0D, ANT_DIV). The internal connection to digital
ground of the control pins pin 9 (DIG1) and pin 10 (DIG2) is disabled (refer to section 4.2), and
they feed the antenna switch signal and its inverse to the differential inputs of the RF Switch
(SW1).
Upon reception of a frame the AT86RF231 selects one antenna during preamble field detection.
The selected antenna is then indicated by register bit ANT_SEL (register 0x0D, ANT_DIV). After
the frame reception is completed, the antenna selection continues searching for new frames on
both antennas. However, the register bit ANT_SEL maintains its previous value (from the last
received frame) until a new SHR has been found, and the selection algorithm locked into one
antenna again. At this time the register bit ANT_SEL is updated again.
For transmission the antenna defined by register bits ANT_CTRL (register 0x0D, ANT_DIV) is
selected. If for example the same antenna is to be used for transmission as being selected for
reception, the antenna must be set using register bits ANT_CTRL, based on the value read from
r e g i s t e r b i t A N T _ S E L . I t i s r e c o m m e n d e d t o r e a d r e g i s t e r b i t A N T _ S E L a f t e r
IRQ_2 (RX_START).
The autonomous search and selection allows the use of Antenna Diversity during reception
even if the microcontroller does currently not control the radio transceiver, for instance in
Extended Operating Mode.
A microcontroller defined selection of a certain antenna can be done by disabling the automated
Antenna Diversity algorithm (ANT_DIV_EN = 0) and selecting one antenna using register bit
ANT_CTRL.
If the AT86RF231 is not in a receive or transmit state, it is recommended to disable register bit
ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF
switch, especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins
DIG1/DIG2 are pulled-down to digital ground.
Due to a different receive algorithm used by the Antenna Diversity algorithm, the correlator
threshold of the receiver has to be adjusted. It is recommended to set register bits PDT_THRES
(register 0x0A, RX_CTRL) to 3.
Register 0x0A (RX_CTRL):
The RX_CTRL controls the sensitivity of the Antenna Diversity Mode
• Bit [7:4] - Reserved
R/W
6
0
Reserved
R/W
5
1
R/W
4
1
R/W
3
0
R/W
2
1
PDT_THRES
R/W
1
1
AT86RF231
R/W
0
1
RX_CTRL
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