AT86RF231-ZU Atmel, AT86RF231-ZU Datasheet - Page 39

• Manufacturer Part Number: AT86RF231-ZU
• Description: IC TXRX ZIGBE/802.15.4/ISM 32QFN
• Manufacturer: Atmel

Specifications of AT86RF231-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Applications: Industrial Monitoring and Control, Wireless Alarm and Security Systems
• Power - Output: -17dBm ~ 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.3mA
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2405 MHz to 2480 MHz
• Interface Type: SPI
• Noise Figure: 6 dB
• Output Power: 20 dB
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 12.3 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Transmitting Current: 11.6mA
• Data Rate: 2Mbps
• Frequency Range: 2.405GHz To 2.48GHz
• Modulation Type: O-QPSK
• Sensitivity Dbm: -101dBm
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 7-2.
7.1.4
7.1.4.1
8111C–MCU Wireless–09/09
TRX_STATE
SLP_TR
Typ. Processing Delay
Number of Octets
Frame Content
TRX_STATE
IRQ
Interrupt latency
IRQ
Basic Operating Mode Timing
Power-on Procedure
Timing of RX_START, AMI and TRX_END Interrupts in Basic Operating Mode
PLL_ON
-16
The following paragraphs depict state transitions and their timing properties. Timing figures are
explained in
page
The power-on procedure to P_ON state is shown in
Figure 7-3.
When the external supply voltage (V
ceiver enables the crystal oscillator (XOSC) and the internal 1.8 V voltage regulator for the
digital domain (DVREG). After t
(CLKM) at default rate of 1 MHz. If CLKM is available the SPI is already enabled and can be
used to control the transceiver. As long as no state change towards state TRX_OFF is per-
formed the radio transceiver remains in P_ON state.
0
Event
State
Block
Time
157.
16 µs
RX_ON
Preamble
Table 7-1 on page 42
Power-on Procedure to P_ON State
4
0
V
P_ON
XOSC, DVREG
DD
on
128
SFD
100
1
160
TR1
PHR
and
BUSY_TX
= 330 µs (typ.), the master clock signal is available at pin 17
1
t
TR1
192
DD
Section 12.4 “Digital Interface Timing Characteristics” on
) is firstly supplied to the AT86RF231, the radio trans-
IRQ_2 (RX_START)
MHR
t
IRQ
7
Figure 7-3 on page
400
BUSY_RX
IRQ_5 (AMI)
CLKM on
MSDU
t
IRQ
m
IRQ_3 (TRX_END)
192+(9+m)*32
FCS
39.
2
AT86RF231
PLL_ON
RX_ON
TRX_END
t
IRQ
Time [µs]
Time [µs]
39