AT86RF231-ZU Atmel, AT86RF231-ZU Datasheet - Page 22

• Manufacturer Part Number: AT86RF231-ZU
• Description: IC TXRX ZIGBE/802.15.4/ISM 32QFN
• Manufacturer: Atmel

Specifications of AT86RF231-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Applications: Industrial Monitoring and Control, Wireless Alarm and Security Systems
• Power - Output: -17dBm ~ 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.3mA
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2405 MHz to 2480 MHz
• Interface Type: SPI
• Noise Figure: 6 dB
• Output Power: 20 dB
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 12.3 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Transmitting Current: 11.6mA
• Data Rate: 2Mbps
• Frequency Range: 2.405GHz To 2.48GHz
• Modulation Type: O-QPSK
• Sensitivity Dbm: -101dBm
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 6-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4 byte PSDU
6.2.3
Figure 6-11. Packet Structure - SRAM Read Access
8111C–MCU Wireless–09/09
/SEL
SCLK
MOSI
MISO
MOSI
MISO
0
SRAM Access Mode
byte 1 (command byte)
0
PHY_STATUS
0
PHY_STATUS
COMMAND
reserved[4:0]
Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6
(TRX_UR). For further details, refer to
Notes
The SRAM access mode allows accessing dedicated bytes within the Frame Buffer. This may
reduce the SPI traffic.
The SRAM access mode is useful, for instance, if a transmit frame is already stored in the Frame
Buffer and dedicated bytes (e.g. sequence number, address field) need to be replaced before
retransmitting the frame. Furthermore, it can be used to access only the LQI value after frame
reception. A detailed description of the user accessible frame content can be found in
9.3 “Frame Buffer” on page
Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the com-
mand byte and must indicate an SRAM access mode according to the definition in
page
space is 0x00 to 0x7F for radio transceiver receive or transmit operations.
On SRAM read access, one or more bytes of read data are transferred on MISO starting with the
third byte of the access sequence (see
• The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by
• To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to
• It is not possible to retransmit received frames without a Frame Buffer read and write access
• For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode
new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no
frame was received in the meanwhile.
Section 11.8 “Dynamic Frame Buffer Protection” on page
cycle.
(TX_ARET) refer to
CSMA-CA Retry” on page
0
19. The following byte indicates the start address of the write or read access. The address
XX
PHR
ADDRESS[6:0]
byte 2 (address)
XX
PSDU 1
XX
Section 7.2.4 “TX_ARET_ON - Transmit with Automatic Retry and
107.
byte 3 (data byte)
64.
DATA[7:0]
XX
PSDU 2
XX
Section 9.3 “Frame Buffer” on page
Figure 6-11 on page
PSDU 3
XX
byte n-1 (data byte)
DATA[7:0]
22).
154.
XX
PSDU 4
XX
AT86RF231
107.
byte n (data byte)
DATA[7:0]
XX
Table 6-2 on
Section
22