AT86RF231-ZU Atmel, AT86RF231-ZU Datasheet - Page 23

• Manufacturer Part Number: AT86RF231-ZU
• Description: IC TXRX ZIGBE/802.15.4/ISM 32QFN
• Manufacturer: Atmel

Specifications of AT86RF231-ZU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
• Applications: Industrial Monitoring and Control, Wireless Alarm and Security Systems
• Power - Output: -17dBm ~ 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.3mA
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2405 MHz to 2480 MHz
• Interface Type: SPI
• Noise Figure: 6 dB
• Output Power: 20 dB
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 12.3 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• Transmitting Current: 11.6mA
• Data Rate: 2Mbps
• Frequency Range: 2.405GHz To 2.48GHz
• Modulation Type: O-QPSK
• Sensitivity Dbm: -101dBm
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 6-12. Packet Structure - SRAM Write Access
Figure 6-13. Example SPI Sequence - SRAM Read Access of a 5 byte Data Package
Figure 6-14. Example SPI Sequence - SRAM Write Access of a 5 byte Data Package
8111C–MCU Wireless–09/09
MOSI
MISO
/SEL
SCLK
MOSI
MISO
/SEL
SCLK
MOSI
MISO
0
byte 1 (command byte)
1
PHY_STATUS
PHY_STATUS
0
PHY_STATUS
COMMAND
COMMAND
reserved[4:0]
On SRAM write access, one or more bytes of write data are transferred on MOSI starting with
the third byte of the access sequence (see
On SRAM read or write accesses do not attempt to read or write bytes beyond the SRAM buffer
size.
As long as /SEL = L, every subsequent byte read or byte write increments the address counter
of the Frame Buffer until the SRAM access is terminated by /SEL = H.
Figure 6-13 on page 23
SRAM access to read and write a data package of 5-byte length respectively.
Notes
• The SRAM access mode is not intended to be used as an alternative to the Frame Buffer
• If the SRAM access mode is used to read PSDU data, the Frame Buffer contains all PSDU
• Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the
access modes (see
data except the frame length byte (PHR). The frame length information can be accessed only
using Frame Buffer access.
SRAM access mode, for further details refer to
109.
0
ADDRESS
ADDRESS
XX
XX
ADDRESS[6:0]
byte 2 (address)
XX
DATA 1
DATA 1
XX
XX
Section 6.2.2 “Frame Buffer Access Mode” on page
and
Figure 6-14 on page 23
byte 3 (data byte)
DATA[7:0]
XX
DATA 2
DATA 2
XX
XX
Figure 6-12 on page
DATA 3
DATA 3
XX
Section 9.3.3 “Interrupt Handling” on page
XX
illustrate an example SPI sequence of a
byte n-1 (data byte)
DATA[7:0]
XX
DATA 4
DATA 4
23).
XX
XX
AT86RF231
20).
byte n (data byte)
DATA 5
DATA 5
DATA[7:0]
XX
XX
XX
23