MC13212 Freescale Semiconductor, MC13212 Datasheet - Page 45
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MC13212
Manufacturer Part Number
MC13212
Description
IC TXRX RF 2.4GHZ FLSH 32K 71LGA
Manufacturer
Freescale Semiconductor
Series
MC1321xr
Datasheet
1.1321XCSK-BDM.pdf
(70 pages)
Specifications of MC13212
Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3dBm
Sensitivity
-92dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
42mA
Current - Transmitting
35mA
Data Interface
PCB, Surface Mount
Memory Size
32kB Flash, 2kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
71-LGA
Mounting Style
SMD/SMT
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC13212
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC13212R2
Manufacturer:
FREESCALE
Quantity:
340
5.7.8
Development support systems in the include the background debug controller (BDC) and the on-chip
debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that provides a
convenient interface for programming the on-chip FLASH and other non-volatile memories. The BDC is
also the primary debug interface for development and allows non-intrusive access to memory data and
traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
Address and data bus signals are not available on external pins (not even in test modes). Debug is done
through commands fed into the MCU via the single-wire background debug interface. The debug module
provides a means to selectively trigger and capture bus information so an external development system can
reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external access to the
address and data signals.
The alternate BDC clock source for HCS08 is the ICGLCLK.
5.7.8.1
Features of the background debug controller (BDC) include:
Features of the debug module (DBG) include:
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Single pin for mode selection and background communications
BDC registers are not located in the memory map
SYNC command to determine target communications rate
Non-intrusive commands for memory access
Active background mode commands for CPU register access
GO and TRACE1 commands
BACKGROUND command can wake CPU from stop or wait modes
One hardware address breakpoint built into BDC
Oscillator runs in stop mode, if BDC enabled
COP watchdog disabled while in active background mode
Two trigger comparators:
— Two address + read/write (R/W) or
— One full address + data + R/W
Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
— Change-of-flow addresses or
— Event-only data
Two types of breakpoints:
— Tag breakpoints for instruction opcodes
— Force breakpoints for any address access
Nine trigger modes:
Development Support
Development Support Features
MC13211/212/213 Technical Data, Rev. 1.8
45