MFRC52301HN1,157 NXP Semiconductors, MFRC52301HN1,157 Datasheet - Page 58

• Manufacturer Part Number: MFRC52301HN1,157
• Description: IC READER 13.56MHZ 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of MFRC52301HN1,157

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935282956157

NXP Semiconductors
MFRC523_34
Product data sheet
PUBLIC
Table 105. TModeReg register bit descriptions
Table 106. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation
Bit
7
6 to 5
4
3 to 0
Bit
Symbol
Access
Symbol
TAuto
TGated[1:0]
TAutoRestart
TPrescaler_Hi[3:0] -
7
All information provided in this document is subject to legal disclaimers.
Rev. 3.5 — 24 September 2010
6
Value Description
1
0
00
01
10
11
1
0
115235
5
the timer starts automatically at the end of the transmission in
all communication modes at all speeds or when InvTxnRFOn
bits are set to logic 1 and the RF field is switched on
when RxMultiple bit in register RxModeReg is logic 0: in
MIFARE mode and ISO/IEC 14443 B at 106 kBd, the timer
stops after the 5
modes, the timer stops after the 4
if the RxMultiple bit is set to logic 1, the timer never stops. In
this case the timer can be stopped by setting the TStopNow
bit in register ControlReg to logic 1
indicates that the timer is not influenced by the protocol
internal timer is runs in gated or non-gated mode
Remark: in gated mode, the Status1Reg register’s TRunning
bit is logic 1 when the timer is enabled by the TModeReg
register bits
these bits do not influence the gating signal
timer automatically restarts its count-down from the 16-bit
timer reload value instead of counting down to zero
timer decrements to 0 and the ComIrqReg register’s
TimerIRq bit is set to logic 1
defines the higher 4 bits of the TPrescaler value
the following formula is used to calculate f
TPrescalEven bit in Demod Reg is set to logic 0:
f
where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo]
(TPrescaler value on 12 bits). The default TPrescalEven is
logic 0
the following formula is used to calculate f
TPrescalEven bit in Demod Reg is set to logic 1:
f
“Timer unit”
Timer
Timer
non-gated mode
gated by pin MFIN
gated by pin AUX1
-
= 13.56 MHz / (2 * TPreScaler + 2); see
= 13.56 MHz / (2 * TPreScaler + 1).
TPrescaler_Lo[7:0]
4
R/W
th
bit (1 start bit, 4 data bits). In all other
3
th
2
bit
Contactless reader IC
MFRC523
© NXP B.V. 2010. All rights reserved.
Timer
Timer
1
Section 8.7
if
if
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