XR16L580IM-F Exar Corporation, XR16L580IM-F Datasheet - Page 11

• Manufacturer Part Number: XR16L580IM-F
• Description: IC UART FIFO 16B 48TQFP
• Manufacturer: Exar Corporation

Specifications of XR16L580IM-F

• Number Of Channels: 1, UART
• Package / Case: 48-TQFP
• Features: *
• Fifo's: 16 Byte
• Protocol: RS232, RS422
• Voltage - Supply: 2.25 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 3.125 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 1
• Uart Features: Selectable RX And TX FIFO Trigger Levels, Automatic Software Flow Control, Complete Modem Interface
• Supply Voltage Range: 2.25V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.4.1
For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at
http://www.exar.com.
The L580 UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit (bit-7) in the MCR register. This bit selects the prescaler to divide the input crystal or external clock
by a factor of 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by
a programmable divisor (via DLL and DLM registers) between 1 and (2
clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver
for data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon
power up.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
clock at 16X sampling rate clock rate. When using a non-standard data rate crystal or external clock, the
divisor value can be calculated for DLL/DLM with the following equation.
2.9
Programmable Baud Rate Generator
F
IGURE
XTAL1
XTAL2
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
Table 3
7. B
AUD
shows the standard data rates available with a 14.7456 MHz crystal or external
R
Crystal
Buffer
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
Osc/
ATE
F
IGURE
G
v c c
g n d
ENERATOR AND
6. E
E x te rn a l C lo c k
Divide by 4
Divide by 1
XTERNAL
Prescaler
Prescaler
R 1
2 K
V C C
P
11
RESCALER
C
LOCK
MCR Bit-7=0
MCR Bit-7=1
(default)
X T A L 1
X T A L 2
C
ONNECTION FOR
Baud Rate
DLL and DLM
Generator
Registers
Logic
16
-1) to obtain a 16X sampling rate
E
Rate Clock to
XTENDED
Transmitter
Sampling
16X
D
ATA
XR16L580
R
ATE