XR16L580IM-F Exar Corporation, XR16L580IM-F Datasheet - Page 14
![IC UART FIFO 16B 48TQFP](/photos/16/10/161019/tqfp-48_sml.jpg)
XR16L580IM-F
Manufacturer Part Number
XR16L580IM-F
Description
IC UART FIFO 16B 48TQFP
Manufacturer
Exar Corporation
Datasheet
1.XR16L580IL24TR-F.pdf
(52 pages)
Specifications of XR16L580IM-F
Number Of Channels
1, UART
Package / Case
48-TQFP
Features
*
Fifo's
16 Byte
Protocol
RS232, RS422
Voltage - Supply
2.25 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
3.125 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
No. Of Channels
1
Uart Features
Selectable RX And TX FIFO Trigger Levels, Automatic Software Flow Control, Complete Modem Interface
Supply Voltage Range
2.25V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16L580IM-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR16L580IM-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. On the falling edge of a
start or a false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start
bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is
validated as a start bit. Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Each of the data, parity and stop bits is sampled at the middle of the bit to prevent false framing. If
there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte
from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status
of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character
or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus
12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
F
2.11
2.11.1
IGURE
9. T
RECEIVER
Receive Holding Register (RHR) - Read-Only
RANSMITTER
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
(Xoff1,2 and Xon1,2 Reg.)
Flow Control Characters
O
16X Clock
PERATION IN
Data Byte
Transmit
FIFO
AND
Transm it Data Shift Register
F
LOW
Transm it
FIFO
(TSR)
14
C
ONTROL
FIFO is Enabled by FCR bit-0=1
M
THR Interrupt (ISR bit-1):
- W hen the TX FIFO falls below the
- W hen the TX FIFO becomes em pty.
ODE
programmed Trigger Level, and
T XF IF O 1
REV. 1.4.1