XR16L580IM-F Exar Corporation, XR16L580IM-F Datasheet - Page 30
![IC UART FIFO 16B 48TQFP](/photos/16/10/161019/tqfp-48_sml.jpg)
XR16L580IM-F
Manufacturer Part Number
XR16L580IM-F
Description
IC UART FIFO 16B 48TQFP
Manufacturer
Exar Corporation
Datasheet
1.XR16L580IL24TR-F.pdf
(52 pages)
Specifications of XR16L580IM-F
Number Of Channels
1, UART
Package / Case
48-TQFP
Features
*
Fifo's
16 Byte
Protocol
RS232, RS422
Voltage - Supply
2.25 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
3.125 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
No. Of Channels
1
Uart Features
Selectable RX And TX FIFO Trigger Levels, Automatic Software Flow Control, Complete Modem Interface
Supply Voltage Range
2.25V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16L580IM-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR16L580IM-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•
•
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
•
•
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output. This bit has no functionality in the 24-QFN and 28-QFN packages except in
internal loopback mode.
•
•
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output. This bit
has no functionality in the 24-QFN package except in internal loopback mode.
•
•
MCR[2]: Invert Infrared RX Data or OP1# (legacy term)
If IrDA mode is enabled by setting MCR[6]=1 and if EFR[4] = 1, this bit acts as ’Invert Infrared RX data’
command. If EFR[4] = 0 or in internal loopback mode, this bit functions like the OP1# in the 16C550.
•
•
In the Internal Loopback Mode, this bit controls the state of the modem input RI# bit in the MSR register as
shown in
MCR[3]: INT Output Enable or OP2# (legacy term)
This bit enables and disables the operation of interrupt output, INT in the Intel mode. It has no function in the
Motorola mode.
•
•
In the Internal Loopback Mode, this bit functions like the OP2# in the 16C550 and is used to set the state of the
modem input CD# bit in the MSR register.
4.8
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
Logic 0 = Select RX input as active-low encoded IrDA data (if IrDA Mode is enabled by setting MCR[6] = 1
and EFR[4] = 1) (default).
Logic 1 = Select RX input as active-high encoded IrDA data (if MCR[6] = 1 and EFR[4] = 1). In this mode, this
bit is write-only.
Logic 0 = INT output disabled (three state mode) (default).
Logic 1 = INT output enabled (active mode).
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
Figure 14
.
30
REV. 1.4.1