XC6SLX16-2CSG324C Xilinx Inc, XC6SLX16-2CSG324C Datasheet - Page 10

• Manufacturer Part Number: XC6SLX16-2CSG324C
• Description: IC FPGA SPARTAN 6 14K 324CSGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX16-2CSG324C

• Total Ram Bits: 589824
• Number Of Logic Elements/cells: 14579
• Number Of Labs/clbs: 1139
• Number Of I /o: 232
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-LFBGA, CSPBGA
• No. Of Macrocells: 14579
• Family Type: Spartan-6
• No. Of Speed Grades: 2
• No. Of I/o's: 232
• Clock Management: DCM, PLL
• Core Supply Voltage Range: 1.14V To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1671

Table 10: Differential I/O Standard DC Input and Output Levels
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
LVDS_33
LVDS_25
BLVDS_25
MINI_LVDS_33
MINI_LVDS_25
LVPECL_33
LVPECL_25
RSDS_33
RSDS_25
TMDS_33
PPDS_33
PPDS_25
DISPLAY_PORT
DIFF_MOBILE_DDR
DIFF_HSTL_I
DIFF_HSTL_II
DIFF_HSTL_III
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_SSTL3_I
DIFF_SSTL3_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL15_II
I/O Standard
LVPECL_33 and TMDS_33 maximum V
When V
LVPECL_25, LVPECL_33, RSDS_25, RSDS_33, PPDS_25, and PPDS_33.
The -1L devices require V
and PPDS_33 I/O standards on inputs. LVPECL_33 is not supported in the -1L devices.
(2)(3)
(2)(3)
(2)(3)
(2)(3)
(2)(3)
(2)(3)
(2)(3)
CCAUX
(2)(3)
(2)(3)
= 3.3V, the DCD can be higher than 5% for V
mV,
Min
100
100
100
200
200
100
100
100
100
150
100
100
190
100
100
100
100
100
100
100
100
100
100
100
100
100
100
CCAUX
V
ID
1000
1000
1200
1260
Max
mV,
600
600
600
600
400
400
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
= 2.5V when using the LVDS_25, LVDS_33, BLVDS_25, LVPECL_25, RSDS_25, RSDS_33, PPDS_25,
V, Min
0.78
0.68
0.68
0.68
0.55
ICM
0.3
0.3
0.3
0.3
0.3
0.2
0.2
0.3
0.8
0.8
1.0
1.0
0.7
0.7
0.3
0.3
0.3
0.3
2.7
0.8
1.0
1.0
is the lower of V (maximum) or V
V
ICM
V, Max mV, Min
3.23
2.8
2.35
2.35
2.35
1.95
1.95
1.95
2.35
1.02
0.95
1.5
1.5
2.3
2.3
0.9
0.9
0.9
1.1
1.1
1.1
1.9
1.9
1.5
1.5
1.1
1.1
(1)
(1)
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
ICM
247
247
240
300
300
100
100
400
100
100
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
< 0.7V when using these I/O standards: LVDS_25, LVDS_33, BLVDS_25,
V
OD
Max
mV,
454
454
460
600
600
400
400
800
400
400
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CCAUX
V
CCO
– (V
V, Min
1.125
1.125
1.0
1.0
1.0
1.0
0.5
0.5
Typical 50% V
Typical 50% V
– 0.405 V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ID
/2)
Inputs only
Inputs only
V
OCM
CCO
V, Max
1.375
1.375
CCO
CCO
1.4
1.4
1.4
1.4
1.4
1.4
– 0.190
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
90% V
V
V
V
V
V
V
V
CCO
CCO
CCO
CCO
CCO
CCO
TT
TT
TT
V, Min
TT
TT
TT
TT
V
+ 0.61 V
+ 0.81 V
+ 0.47 V
OH
–
–
–
–
–
–
–
–
–
–
–
+ 0.6
+ 0.8
+ 0.6
+ 0.4
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
– 0.4
CCO
10% V
V
V
V
V
TT
TT
TT
V, Max
TT
TT
TT
TT
V
0.4
0.4
0.4
0.4
0.4
0.4
– 0.61
– 0.81
– 0.47
–
–
–
–
–
–
–
–
–
–
–
OL
– 0.6
– 0.8
– 0.6
– 0.4
CCO
10