XC6SLX16-2CSG324C Xilinx Inc, XC6SLX16-2CSG324C Datasheet - Page 65

IC FPGA SPARTAN 6 14K 324CSGBGA

XC6SLX16-2CSG324C

Manufacturer Part Number
XC6SLX16-2CSG324C
Description
IC FPGA SPARTAN 6 14K 324CSGBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXr

Specifications of XC6SLX16-2CSG324C

Total Ram Bits
589824
Number Of Logic Elements/cells
14579
Number Of Labs/clbs
1139
Number Of I /o
232
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-LFBGA, CSPBGA
No. Of Macrocells
14579
Family Type
Spartan-6
No. Of Speed Grades
2
No. Of I/o's
232
Clock Management
DCM, PLL
Core Supply Voltage Range
1.14V To
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1671

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC6SLX16-2CSG324C
Manufacturer:
XILINX44
Quantity:
1 260
Part Number:
XC6SLX16-2CSG324C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC6SLX16-2CSG324C
Manufacturer:
XILINX
0
Part Number:
XC6SLX16-2CSG324C
0
Company:
Part Number:
XC6SLX16-2CSG324C
Quantity:
41
Part Number:
XC6SLX16-2CSG324CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC6SLX16-2CSG324CES
Manufacturer:
XILINX
0
Table 71: Global Clock Setup and Hold With PLL in System-Synchronous Mode
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.
T
PSPLL
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
IFF = Input Flip-Flop or Latch
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Symbol
/ T
PHPLL
No Delay Global Clock and IFF
System-Synchronous Mode
Description
(2)
with PLL in
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
Device
–0.03
1.37/
1.37/
1.33/
1.65/
1.70/
1.55/
1.57/
1.77/
1.80/
1.44/
1.51/
1.39/
1.41/
0.25
0.21
0.28
0.28
0.18
0.18
0.21
0.21
0.32
0.32
0.49
0.49
-3
(1)
–0.02
1.48/
1.53/
1.71/
1.71/
1.64/
1.64/
1.89/
1.89/
1.52/
1.52/
1.48/
1.48/
0.21
0.28
0.28
0.18
0.18
0.21
0.21
0.32
0.32
0.49
0.49
Speed Grade
N/A
-3N
–0.02
1.52/
1.52/
1.60/
1.91/
1.91/
1.75/
1.75/
2.13/
2.13/
1.70/
1.70/
1.67/
1.67/
0.41
0.26
0.28
0.28
0.18
0.18
0.21
0.21
0.32
0.32
0.49
0.49
-2
2.07/
2.07/
1.57/
2.44/
2.02/
2.46/
1.78/
1.94/
0.69
0.69
0.48
0.76
0.90
0.53
0.86
0.94
N/A
N/A
N/A
N/A
N/A
-1L
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
65

Related parts for XC6SLX16-2CSG324C