SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 16

• Manufacturer Part Number: SPEAR320-2
• Description: IC MPU ARM9 289LFBGA
• Manufacturer: STMicroelectronics
• Series: SPEAr®r

Specifications of SPEAR320-2

• Processor Type: ARM Microprocessor
• Speed: 333MHz
• Voltage: 1.14 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 289-LFBGA
• Processor Series: SPEAr320
• Core: ARM926EJ-S
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Data Ram Size: 8 KB
• Interface Type: I2C, UART, USB, Serial
• Number Of Programmable I/os: 102
• Number Of Timers: 4
• Program Memory Size: 32 KB
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-10843

Architecture overview
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Main features:
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CAN controller
SPEAr320 has two CAN controllers for interfacing CAN 2.0 networks.
Main features:
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USB2 host controller
SPEAr320 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks:
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Supports the default Media Independent Interface (MII) defined in the IEEE 802.3
specifications.
Supports 10/100 Mbps data transfer rates
Local FIFO available (4 Kbyte RX, 2 Kbyte TX)
Supports both half-duplex and full-duplex operation. In half-duplex operation,
CSMA/CD protocol is provided
Programmable frame length to support both standard and jumbo Ethernet frames with
size up to 16 Kbytes
32/64/128-bit data transfer interface on system-side.
A variety of flexible address filtering modes are supported
A set of control and status registers (CSRs) to control GMAC core operation
Native DMA with single-channel transmit and receive engines, providing 32/64/128-bit
data transfers
DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining
An AHB slave acting as programming interface to access all CSRs, for both DMA and
GMAC core subsystems
An AHB master for data transfer to system memory
32-bit AHB master bus width, supporting 32, 64, and 128-bit wide data transactions
It supports both big-endian and little-endian.
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 MBit/s
16 message objects(136 X 16 message RAM)
Each message object has its own identifier mask
Maskable interrupt
Programmable loop-back mode for self-test operation
Disabled automatic retransmission mode for time triggered CAN applications
EHCI capable of managing high-speed transfers (HS mode, 480 Mbps)
OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps)
Local 2-Kbyte FIFO
Local DMA
Integrated USB2 transceiver (PHY)
Doc ID 16755 Rev 4
SPEAr320