SPEAR320-2 STMicroelectronics, SPEAR320-2 Datasheet - Page 22
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SPEAR320-2
Manufacturer Part Number
SPEAR320-2
Description
IC MPU ARM9 289LFBGA
Manufacturer
STMicroelectronics
Series
SPEAr®r
Datasheet
1.SPEAR320-2.pdf
(76 pages)
Specifications of SPEAR320-2
Processor Type
ARM Microprocessor
Speed
333MHz
Voltage
1.14 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
289-LFBGA
Processor Series
SPEAr320
Core
ARM926EJ-S
Data Bus Width
16 bit
Maximum Clock Frequency
333 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Data Ram Size
8 KB
Interface Type
I2C, UART, USB, Serial
Number Of Programmable I/os
102
Number Of Timers
4
Program Memory Size
32 KB
Program Memory Type
ROM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-10843
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Architecture overview
3.22
3.23
3.23.1
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8-channel ADC
Main features:
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System controller
The System Controller provides an interface for controlling the operation of the overall
system.
Main features:
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Power saving system mode control
Using three mode control bits, the system controller switch the SPEAr320 to any one of four
different modes: DOZE, SLEEP, SLOW and NORMAL.
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Successive approximation conversion method
10-bit resolution @1 Msps
Hardware supporting up to 13.5 bits resolution at 8 ksps by oversampling and
accumulation
Eight analog input (AIN) channels, ranging from 0 to 2.5 V
INL ± 1 LSB, DNL ± 1 LSB
Programmable conversion speed, (min. conversion time is 1 µs)
Programmable averaging of results from 1 (No averaging) up to 128
Programmable auto scan for all the eight channels.
Power saving system mode control
Crystal oscillator and PLL control
Configuration of system response to interrupts
Reset status capture and soft reset generation
Watchdog and timer module clock enable
SLEEP mode: In this mode the system clocks, HCLK and CLK, are disabled and the
System Controller clock SCLK is driven by a low speed oscillator (nominally 32768 Hz).
When either a FIQ or an IRQ interrupt is generated (through the VIC) the system enters
DOZE mode. Additionally, the operating mode setting in the system control register
automatically changes from SLEEP to DOZE.
DOZE mode: In this mode the system clocks, HCLK and CLK, and the System
Controller clock SCLK are driven by a low speed oscillator. The System Controller
moves into SLEEP mode from DOZE mode only when none of the mode control bits
are set and the processor is in Wait-for-interrupt state. If SLOW mode or NORMAL
mode is required the system moves into the XTAL control transition state to initialize the
crystal oscillator.
SLOW mode: During this mode, both the system clocks and the System Controller
clock are driven by the crystal oscillator. If NORMAL mode is selected, the system goes
into the "PLL control" transition state. If neither the SLOW nor the NORMAL mode
control bits are set, the system goes into the "Switch from XTAL" transition state.
NORMAL mode: In NORMAL mode, both the system clocks and the System Controller
clock are driven by the PLL output. If the NORMAL mode control bit is not set, then the
system goes into the "Switch from PLL" transition state.
Doc ID 16755 Rev 4
SPEAr320