WPIXF1104BE.B1-993991 Cortina Systems Inc, WPIXF1104BE.B1-993991 Datasheet
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Cortina Systems Ethernet Media Access Controller Datasheet ® The Cortina Systems IXF1104 4-Port Gigabit Ethernet Media Access Controller (IXF1104 MAC) supports IEEE 802.3* 10/100/1000 Mbps applications. The IXF1104 MAC supports a System Packet Interface Phase 3 (SPI3) system interface to ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Revision History • Updated Figure 39, 1000BASE-T Receive Interface Timing, on page • Updated the Tcdwd and Tcdrh parameter values in • Updated the Tdatd, Tlath and Tlatl parameter values in ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Page # Description N/A First release of this document from Cortina Systems, Inc. Page # Description page 69 Modified Figure 8, Ethernet Frame Format page 130 Table 44, RGMII Power Added ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Revision Date: August 1, 2005 (Sheet Page # Description Modified Table 94, PHY Control ($ Port Index + 0x60) page 173 register default value]. Modified Table 95, PHY ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Page # Description Modified Table 1 “Ball List in Alphanumeric Order by Signal Changed A10 from VCC to VDD Changed C12 from VCC to VDD Changed D11 from VCC to VDD ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Page # Description 69 Added note under Table 22 “CRC Errored Packets Drop Enable Added new Section 5.1.2, “Flow Control” 69 Format”, and Figure 9 “PAUSE Frame Replaced Section 5.1.2.1.5, “Transmit ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Page # Description 123 Modified Table 37 “Byte Swapper Behavior” 123 Modified second paragraph under 126 Modified Figure 33 “SPI3 Interface Loopback 126 Added note under Section 5.11.2, “Line Side Interface ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Page # Description Modified Table 113 “RX FIFO High Watermark Port 0 193 ($0x581)”, Table 115 “RX FIFO High Watermark Port 2 Port 3 ($0x583)” [changed bits 11:0 description]. Renamed and ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Page # Description 87 Modified Table 17 “IXF1104-to-Optical Module Interface Connections” 65 Modified first paragraph under 87 Modified Section 5.8.2.1, “High-Speed Serial 100 Modified Figure 27 “Microprocessor — External and Internal ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Revision Date: April 2001 – December 2002 Page # Description Internal releases. ® Cortina Systems IXF1104 4-Port Gigabit Ethernet Media Access Controller Revisions 001 through 004 Page 11 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Contents 1.0 Introduction.................................................................................................................................. 21 1.1 What You Will Find in This Document ................................................................................ 21 1.2 Related Documents ............................................................................................................ 21 2.0 General Description .................................................................................................................... 22 3.0 Ball Assignments and Ball List Tables ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.5 MDIO Control and Interface................................................................................................ 95 5.5.1 MDIO Address ....................................................................................................... 96 5.5.2 MDIO Register Descriptions .................................................................................. 96 5.5.3 Clear When Done .................................................................................................. 96 5.5.4 MDC Generation.................................................................................................... 96 5.5.5 Management Frames............................................................................................. 96 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.1 DC Specifications ............................................................................................................. 128 7.1.1 Undershoot / Overshoot Specifications ............................................................... 129 7.1.2 RGMII Electrical Characteristics .......................................................................... 130 7.2 SPI3 AC Timing Specifications ......................................................................................... 130 7.2.1 Receive Interface Timing ..................................................................................... 130 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 List of Figures 1 Block Diagram ............................................................................................................................... 22 2 Internal Architecture ...................................................................................................................... 23 3 552-Ball Assignments (Top View) ................................................................................................. 24 4 Interface Signals ........................................................................................................................... 37 5 Power Supply Sequencing ............................................................................................................ 61 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 50 JTAG AC Timing.......................................................................................................................... 145 51 System Reset AC Timing ............................................................................................................ 146 52 LED AC Interface Timing............................................................................................................. 147 53 Memory Overview Diagram ......................................................................................................... 148 54 Register Overview Diagram......................................................................................................... 149 55 CBGA ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 List of Tables 1 Ball List in Alphanumeric Order by Signal Name........................................................................... 25 2 Ball List in Alphanumeric Order by Ball Location........................................................................... 30 3 SPI3 Interface Signal Descriptions ................................................................................................ 38 4 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 50 SerDes Timing Parameters ......................................................................................................... 138 51 MDIO Timing Parameters............................................................................................................ 140 Timing Characteristics..................................................................................................... 141 53 CPU Interface AC Signal Parameters ......................................................................................... 143 54 Transmit Pause Control ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 101 Auto-Negotiation Next Page Transmit ($ Port Index + 0x67) ...................................................... 179 102 Port Enable ($0x500)................................................................................................................... 180 103 Interface Mode ($0x501) ............................................................................................................. 180 104 Link LED Enable ($0x502)........................................................................................................... 181 105 MAC ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 152 Optical Module Status Ports 0-3 ($0x799)................................................................................... 211 153 Optical Module Control Ports ($0x79A)............................................................................... 211 2 154 I C Control Ports ($0x79B).................................................................................................. 212 2 155 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 1.0 Introduction This document contains information on the Cortina Systems Ethernet Media Access Controller (IXF1104 MAC), a four-port Gigabit Media Access Controller that supports IEEE 802.3 10/100/1000 Mbps applications from Cortina ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 2.0 General Description The IXF1104 MAC provides 4.0 Gbps interface to four individual 10/100/1000 Mbps full-duplex or 10/100 Mbps half-duplex-capable Ethernet Media Access Controllers (MACs). The network processor ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 2 Internal Architecture CPU Interface SPI3 Interface Clock Control Block ® Cortina Systems IXF1104 4-Port Gigabit Ethernet Media Access Controller RMON Statistics Packet TX Buffer RX Packet TX Buffer RX ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 3.0 Ball Assignments and Ball List Tables 3.1 Ball Assignments See Figure 3, Table 1, Ball List in Alphanumeric Order by Signal Name, on page Table 2, Ball List in Alphanumeric ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 3.2 Ball List Tables 3.2.1 Balls Listed in Alphabetic Order by Signal Name Table 1 shows the ball locations and signal names arranged in alphanumeric order by signal name. The following ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Signal Name Location GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Signal Name Location 2 PTPA 2 RDAT_0 2 RDAT_1 2 RDAT_2 2 RDAT_3 2 RDAT_4 2 RDAT_5 2 RDAT_6 2 RDAT_7 2 RDAT_8 2 RDAT_9 2 RDAT_10 2 RDAT_11 2 RDAT_12 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Signal Name Location 2 TADR1 TCLK 2 TDAT0 2 TDAT1 2 TDAT2 2 TDAT3 2 TDAT4 2 TDAT5 2 TDAT6 2 TDAT7 2 TDAT8 2 TDAT9 2 TDAT10 2 TDAT11 2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Signal Name Location TXPAUSE_ADD2 TXPAUSEFR UPX_ADD0 UPX_ADD1 UPX_ADD2 UPX_ADD3 UPX_ADD4 UPX_ADD5 UPX_ADD6 UPX_ADD7 UPX_ADD8 UPX_ADD9 UPX_ADD10 UPX_BADD0 UPX_BADD1 uPx_Cs_L UPX_DATA0 UPX_DATA1 UPX_DATA2 UPX_DATA3 UPX_DATA4 UPX_DATA5 UPX_DATA6 UPX_DATA7 UPX_DATA8 UPX_DATA9 UPX_DATA10 UPX_DATA11 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Signal Name Location VDD3 VDD3 VDD4 VDD4 VDD4 VDD4 VDD4 VDD4 VDD4 VDD4 VDD4 VDD4 VDD4 VDD4 VDD4 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 VDD5 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Ball Signal Name Location A16 RERR_0 A17 RDAT_8 A18 RENB_1 A19 RFCLK A20 AVDD1P8_1 A21 GND A22 No Ball A23 No Ball A24 No Ball B1 No Ball B2 No Ball ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Ball Signal Name Location F13 VDD3 F14 RDAT_7 F15 GND F16 RDAT_12 F17 VDD3 F18 RDAT_15 F19 GND F20 RPRTY_3 F21 VDD F22 RVAL_3 F23 GND F24 RDAT_31 G1 TDAT9 G2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Ball Signal Name Location L10 GND L11 VDD L12 GND L13 GND L14 VDD L15 GND L16 VDD L17 UPX_DATA31 L18 NC L19 NC L20 GND L21 NC L22 LED_LATCH 2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Ball Signal Name Location T10 GND T11 VDD T12 VDD5 T13 VDD4 T14 VDD T15 GND T16 RXD4_3 T17 RXD5_3 T18 RXD6_3 T19 RXD7_3 T20 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Ball Signal Name Location AA4 GND AA5 CRS_0 AA6 VDD AA7 TXD4_1 AA8 GND AA9 CRS_1 AA10 VDD AA11 RXD6_1 AA12 GND AA13 GND AA14 TXD4_3 AA15 VDD AA16 TXD6_3 AA17 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 4.0 Ball Assignments and Signal Descriptions 4.1 Naming Conventions 4.1.1 Signal Name Conventions Signal names begin with a Signal Mnemonic, and can also contain one or more of the following designations: ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 4 Interface Signals SPHY TDAT[7:0]_0:3 TFCLK TENB_0:3 TERR_0:3 TPRTY_0:3 TSOP_0:3 TEOP_0:3 TADR[1:0] DTPA_0:3 SPI3 Interface RDAT[7:0]_0:3 RFCLK RENB_0:3 RVAL_0:3 RERR_0:3 RPRTY_0:3 RSOP_0:3 REOP_0:3 JTAG Interface MDIO Interface Pause Control Interface ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 3 SPI3 Interface Signal Descriptions (Sheet Signal Name MPHY SPHY TDAT31 TDAT7_3 TDAT30 TDAT6_3 TDAT29 TDAT5_3 TDAT28 TDAT4_3 TDAT27 TDAT3_3 TDAT26 TDAT2_3 TDAT25 TDAT1_3 TDAT24 TDAT0_3 TDAT23 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 3 SPI3 Interface Signal Descriptions (Sheet Signal Name MPHY SPHY TENB_0 TENB_0 TENB_1 TENB_2 TENB_3 TERR_0 TERR_0 TERR_1 TERR_2 TERR_3 TSOP_0 TSOP_0 TSOP_1 TSOP_2 TSOP_3 TEOP_0 TEOP_0 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 3 SPI3 Interface Signal Descriptions (Sheet Signal Name MPHY SPHY TMOD1 NA TMOD0 TSX NA TADR1 TADR1 TADR0 TADR0 DTPA_0 DTPA_0 DTPA_1 DTPA_1 DTPA_2 DTPA_2 DTPA_3 DTPA_3 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 3 SPI3 Interface Signal Descriptions (Sheet Signal Name MPHY SPHY STPA NA PTPA PTPA ® Cortina Systems IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Type Standard ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 3 SPI3 Interface Signal Descriptions (Sheet Signal Name MPHY SPHY RDAT31 RDAT7_3 RDAT30 RDAT6_3 RDAT29 RDAT5_3 RDAT28 RDAT4_3 RDAT27 RDAT3_3 RDAT26 RDAT2_3 RDAT25 RDAT1_3 RDAT24 RDAT0_3 RDAT23 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 3 SPI3 Interface Signal Descriptions (Sheet Signal Name MPHY SPHY RENB_0 RENB_0 RENB_1 RENB_2 RENB_3 RERR_0 RERR_0 RERR_1 RERR_2 RERR_3 ® Cortina Systems IXF1104 4-Port Gigabit Ethernet ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 3 SPI3 Interface Signal Descriptions (Sheet Signal Name MPHY SPHY RVAL_0 RVAL_0 RVAL_1 RVAL_2 RVAL_3 RSOP_0 RSOP_0 RSOP_1 RSOP_2 RSOP_3 ® Cortina Systems IXF1104 4-Port Gigabit Ethernet ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 3 SPI3 Interface Signal Descriptions (Sheet Signal Name MPHY SPHY REOP_0 REOP_0 REOP_1 REOP_2 REOP_3 RMOD1 NA RMOD0 RSX NA ® Cortina Systems IXF1104 4-Port Gigabit Ethernet ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 4 SerDes Interface Signal Descriptions Signal Name Ball Designator TX_P_0 Y13 TX_P_1 AD13 TX_P_2 W16 TX_P_3 AC18 TX_N_0 Y14 TX_N_1 AD14 TX_N_2 Y16 TX_N_3 AD18 RX_P_0 P22 RX_P_1 V22 RX_P_2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 5 GMII Interface Signal Descriptions (Sheet Signal Name TXD7_0 TXD6_0 TXD5_0 TXD4_0 TXD3_0 TXD2_0 TXD1_0 TXD0_0 TXD7_1 TXD6_1 TXD5_1 TXD4_1 TXD3_1 TXD2_1 TXD1_1 TXD0_1 TXD7_2 TXD6_2 TXD5_2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 5 GMII Interface Signal Descriptions (Sheet Signal Name RXD7_0 RXD6_0 RXD5_0 RXD4_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 RXD7_1 RXD6_1 RXD5_1 RXD4_1 RXD3_1 RXD2_1 RXD1_1 RXD0_1 RXD7_2 RXD6_2 RXD5_2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 6 RGMII Interface Signal Descriptions (Sheet Ball Signal Name Designator TXC_0 AA1 TXC_1 AD7 TXC_2 AC20 TXC_3 AB14 TD3_0 AA3 TD2_0 Y3 TD1_0 Y2 TD0_0 Y1 TD3_1 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 6 RGMII Interface Signal Descriptions (Sheet Ball Signal Name Designator RXC_0 V4 RXC_1 AD11 RXC_2 AA24 RXC_3 V23 RD3_0 Y7 RD2_0 W7 RD1_0 V7 RD0_0 V8 RD3_1 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 7 CPU Interface Signal Descriptions (Sheet Ball Signal Name Designator UPX_ADD10 UPX_ADD9 U3 UPX_ADD8 UPX_ADD7 UPX_ADD6 UPX_ADD5 U1 UPX_ADD4 UPX_ADD3 R1 UPX_ADD2 UPX_ADD1 N1 UPX_ADD0 UPX_BADD1 W3 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 7 CPU Interface Signal Descriptions (Sheet Ball Signal Name Designator UPX_RDY_L M1 UPX_WIDTH1 UPX_WIDTH0 U16 Table 8 Transmit Pause Control Interface Signal Descriptions Signal Name Designator TXPAUSEADD2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 9 Optical Module Interface Signal Descriptions (Sheet Signal Name Designator TX_DISABLE_0 TX_DISABLE_1 TX_DISABLE_2 TX_DISABLE_3 MOD_DEF_0 MOD_DEF_1 MOD_DEF_2 MOD_DEF_3 RX_LOS_0 RX_LOS_1 RX_LOS_2 RX_LOS_3 TX_FAULT_0 TX_FAULT_1 TX_FAULT_2 TX_FAULT_3 RX_LOS_INT ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 9 Optical Module Interface Signal Descriptions (Sheet Signal Name Designator MOD_DEF_INT 2 I C_CLK DATA_0 DATA_1 DATA_2 2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 12 JTAG Interface Signal Descriptions Signal Name Designator TCLK TMS TDI TDO TRST_L Table 13 System Interface Signal Descriptions Signal Name Designator CLK125 SYS_RES_L Table 14 Power Supply Signal Descriptions ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 14 Power Supply Signal Descriptions (Sheet Signal Name A10 D11 F21 J14 K17 VDD L14 P14 R17 U10 AA6 B4 F8 VDD2 J12 M12 B13 F13 VDD3 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 15 Line Side Interface Multiplexed Balls (Sheet Copper Mode GMII Signal RGMII Signal TXD[7:5]_0 TXD[7:5]_1 NC TXD[7:5]_2 TXD[7:5]_3 TX_EN_0:3 TX_CTL_0:3 TX_ER_0:3 NC RXC_0:3 RXC_0:3 RXD[3:0]_0 RD[3:0]_0 RXD[3:0]_1 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 16 SPI3 MPHY/SPHY Interface (Sheet SPI3 Signals MPHY SPHY TDAT[31:24] TDAT[7:0]_3 TDAT[23:16] TDAT[7:0]_2 TDAT[15:8] TDAT[7:0]_1 TDAT[7:0] TDAT[7:0]_0 TFCLK TFCLK TPRTY_0 TPRTY_0 GND TPRTY_1 GND TPRTY_2 GND TPRTY_3 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 16 SPI3 MPHY/SPHY Interface (Sheet SPI3 Signals MPHY SPHY RDAT[31:24] RDAT[7:0]_3 RDAT[23:16] RDAT[7:0]_2 RDAT[15:8] RDAT[7:0]_1 RDAT[7:0] RDAT[7:0]_0 RFCLK RFCLK RPRTY_0 RPRTY_0 NC RPRTY_1 NC RPRTY_2 NC RPRTY_3 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 4.5 Ball State During Reset Table 17 Definition of Output and Bi-directional Balls During Hardware Reset (Sheet Interface Ball Name DTPA_0:3 STPA PTPA RDAT[31:0] RVAL_0:3 SPI3 RERR_0:3 RPRTY_0:3 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 17 Definition of Output and Bi-directional Balls During Hardware Reset (Sheet Interface Ball Name TX_FAULT_INT RX_LOS_INT Optical MOD_DEF_INT Module 2 I C_CLK 2 I C_DATA_0:3 Note: Z ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 18 Power Supply Sequencing Power Supply VDD, AVDD1P8_1, AVDD1P8_2 VDD4, VDD5, AVDD2P5_1, AVDD2P5_2 1. The value of 10 µs given is a nominal value only. The exact time difference between ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 6 Analog Power Supply Filter Network 2 1.8 V Table 20 Analog Power Balls Signal Name AVDD1P8_1 AVDD2P5_1 AVDD1P8_2 AVDD2P5_2 ® Cortina Systems IXF1104 4-Port Gigabit Ethernet Media ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.0 Functional Descriptions 5.1 Media Access Controller (MAC) The IXF1104 MAC main functional block consists of four independent 10/100/1000 Mbps Ethernet MACs, which support interfaces for fiber and copper connectivity. • ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 The IXF1104 MAC operates only in full-duplex mode at 1000 Mbps rates on both SerDes and GMII interface connections. The IXF1104 MAC is capable of operation at 1000 Mbps, full-duplex in ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.1.1.3.3 Filter Broadcast Packets This feature is enabled when bit 2 of the Any broadcast frame received in this mode is marked by the MAC to be dropped. The frame is ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 21 CRC Errored Packets Drop Enable Behavior RX FIFO CRC Error ErroredFrame 1 Pass Drop Enable See Table 90, RX Packet Filter Control ($ Port_Index ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 In half-duplex operation, the MAC generates collisions instead of sending pause frames to manage the incoming traffic from the link partner 5.1.2.1 802.3x Flow Control (Full-Duplex Operation) The IEEE 802.3x standard ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 8 Ethernet Frame Format 7 Number of bytes Preamble 64 yte Minimum / 1518 bytes Maximum Note: Figure 9 PAUSE Frame Format An IEEE 802.3 MAC PAUSE frame is identified ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 • Pause Threshold is the amount of time, measured in multiples of 512 bit times, prior to the expiration of the Pause Length that the MAC transmits another Pause frame to ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 22 Valid Decodes for TXPAUSEADD[2:0] TXPAUSEADD_2:0 0x0 0x1 0x2 0x3 0x4 0x5 to 0x6 0x7 Figure 10 Transmit Pause Control Interface TXPAUSEFR TXPAUSEADD0 TXPAUSEADD1 TXPAUSEADD2 This example shows the following ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 The IXF1104 MAC provides complete flexibility in line-side connectivity by offering RGMII, integrated SerDes, and GMII. 5.1.3.1 Configuration The memory maps through Table 68, Optical Module Registers ($ 0x799 - 0x79F), ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 23 Operational Mode Configuration Registers (Sheet Register Register Name Address 0x500 Bit 0 – Port 0 Port Enable Bit 1 – Port 1 ($0x500) Bit 2 – ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.1.4.2 Determining If Link Is Established in Auto-Negotiation Mode A valid link is established when the AN_complete bit is set and the RX_Sync bit reports that synchronization has occurred. Both register ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.1.5.2 Duplex The MAC supports full-duplex or half-duplex depending on the line-side interface that is configured by the MAC IF Mode and RGMII Speed ($ Port_Index + 0x10) The duplex of ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 • TxExcessiveLengthDrop (Addr: Port_Index + 0x53) • TxCRCError (Addr: Port_Index + 0x56) The IXF1104 MAC checks the CRC for all legal-length jumbo frames (frames between 1519 and the Max Frame Size). ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 SPI3 interface before the EOP is received. Packets sizes below this threshold are treated as “store and forward.” Once a packet size exceeds the RX FIFO transfer threshold, it can no ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 24 RMON Additional Statistics (Sheet RMON Ethernet Statistics Group 1 Statistics etherStatsPkts etherStatsBroadcastPkts etherStatsMulticastPkts etherStatsCRCAlignErrors etherStatsUndersizedPkts etherStatsOversizePkts etherStatsFragments etherStatsJabbers etherStatsCollisions etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets Note: The RMON specification ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 24 RMON Additional Statistics (Sheet RMON Ethernet Statistics Group 1 Statistics etherStatsPkts256to511Octets etherStatsPkts512to1023Octets etherStatsPkts1023to1518 Octets etherStatOwner etherStatsStatus Note: The RMON specification requires that this is, “The total ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 packet is equal to the byte position where the invalid symbol was. No packet fragments are seen at the next packet transfer. • Issue: If the invalid 10-bit code is inserted ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 In the receive direction, the IXF1104 MAC specifies the selected port by sending the address on the RDAT[1:0] bus marked with the RSX signal active and RVAL signal inactive. All subsequent ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 11 MPHY Transmit Logical Timing TFCLK TENB TSOP TEOP TMOD [1:0] TERR TSX TDAT 0000 B0-B3 [31:0] TPRTY 1. Applies to all transmit packet available signals (STPA, PTPA, DTPA_0:3). 5.2.2.2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 13 MPHY 32-Bit Interface Network Processor TFCLK TDAT[31:0] TMOD[1:0] TPRTY TSOP TEOP TERR DTPA_0:3 TADR[1:0] RFCLK RENB RDAT[31:0] RMOD[1:0] RPRTY RSOP REOP RERR 5.2.2.3 Clock Rates In MPHY mode, the ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.2.2.5 SPHY Mode The SPHY operation mode is selected when bit 21 of the Global Configuration ($0x700), on page 203 operation for the IXF1104 MAC SPI3 interface. 5.2.2.5.1 Data Path The ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 14 SPHY Transmit Logical Timing TFCLK TENB TSOP TEOP TERR TDAT B0 [7:0] TPRTY 5.2.2.8 Receive Timing (SPHY) A packet is received when RSOP is asserted to indicate the data ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 16 SPHY Connection for Two IXF1104 MAC Ports (8-Bit Interface) 5.2.2.8.1 Clock Rates The TFCLK and RFCLK can be independent of each other in SPHY mode operation. TFCLK and RFCLK ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.2.2.8.2 Parity The IXF1104 MAC can be odd or even (the IXF1104 MAC defaults to odd) when calculating parity on the data bus. This can be changed to accommodate even parity ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 • Dedicated per port Direct Transmit Packet Available (DTPA) • Selected-PHY Transmit Packet Available (STPA), which is based on the current in-band port address in MPHY mode. • Polled-PHY Transmit packet ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 This function is enabled by writing the appropriate data to the Strip Enable ($0x5B3) A standard 1518-byte Ethernet packet occupies 379 long words (four bytes) with two additional bytes left over ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 17 MAC GMII Interconnect 5.3.1 GMII Signal Multiplexing The GMII balls are reassigned when using the RGMII mode or fiber mode. Side Interface Multiplexed Balls, on page 56 modes. See ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 25 GMII Interface Signal Definitions IXF1104 MAC GMII Standard Signal TXC_0 TXC_1 GTX_CLK TXC_2 TXC_3 TXD[7:0]_0 TXD[7:0]_1 TXD[7:0]_2 TXD[7:0]_3 TX_EN_0 TX_EN_1 TX_EN_2 TX_EN_3 TX_ER_0 TX_ER_1 TX_ER_2 TX_ER_3 RXC_0 RXC_1 RXC_2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.4 Reduced Gigabit Media Independent Interface (RGMII) The IXF1104 MAC supports the RGMII interface standard as defined in the RGMII Version 1.2 specification. The RGMII interface is an alternative to the ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.4.3 TX_ER and RX_ER Coding To reduce interface power, the transmit error condition (TX_ER) and the receive error condition (RX_ER) are encoded on the RGMII interface to minimize transitions during normal ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 19 TX_CTL Behavior TXC_0:3 (at Transmitter) TD[3:0]_0:3 TX_CTL_0:3 TXC_0:3 (at Transmitter) TD[3:0]_0:3 TX_CTL_0:3 Figure 20 RX_CTL Behavior RXC_0:3 (at PHY) RD[3:0]_0:3 RX_CTL_0:3 RXC_0:3 (at PHY) RD[3:0]_0:3 RX_CTL_0:3 ® Cortina Systems ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.4.3.1 In-Band Status Carrier Sense (CRS) is generated by the PHY when a packet is received from the network interface. CRS is indicated when: • RXDV = true. • RXDV = ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.5.1 MDIO Address The 5-bit PHY address for the MDIO transactions can be set in the ($0x680). Bits 5:2 of the PHY address are fixed to a value of 0. Bits ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 21 Management Frame Structure (Single-Frame Format) 5.5.6 Single MDI Command Operation The Management Data Interface is accessed through the and the MDIO Single Read and Write Data setting Register 0, ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 22 MDI State Cnt > (Cnt = 16 and Cnt = 16 And ® Cortina Systems IXF1104 4-Port Gigabit Ethernet Media Access ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.5.8 Autoscan Operation The autoscan function allows the 32 registers in each external PHY (up to four stored internally in the IXF1104 MAC. Autoscan is enabled by setting bit ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 The SerDes receive interface receives serialized data at 1.25 GHz. The interface is differential with two signals for the receive operation. The equalizer receives a differential signal that is equalized for ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.6.2.3 Receiver Operational Overview The receiver structure performs Clock and Data Recovery (CDR) on the incoming serial data stream. The quality of this operation is a dominant factor for the Bit ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 23 SerDes Receiver Jitter Tolerance 16 ui 10 Note Unit interval. 5.6.2.6 Transmit Jitter The SerDes core total transmit jitter, including contributions from the ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.7 Optical Module Interface This section describes the connection of the IXF1104 MAC ports to an Optical Module Interface and details the minimal connections that are supported for correct operation. The ...
Page 104
IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.7.2 Functional Descriptions 5.7.2.1 High-Speed Serial Interface These signals are responsible for transfer of the actual data at 1.25 Gbps. Specifications, on page 128 differentially. The following signals are required to ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 The status of each bit (one for each port) is found in ($0x799) bits [23:20]. Any change in the state of these bits causes a logic Low level on the RX_LOS_INT ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 The specific interface in the IXF1104 MAC supports only a subset of the full I²C interface, and only the features required to support the Optical Module Interfaces are implemented. This leads ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 2 Figure Random Read Transaction C_Data Line DON'T CARE bit for 1k) Note: Only one optical ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 the I C Control Ports ($0x79B) complete. 6. The data is written through the CPU interface. The CPU must poll the Write_Complete bit until it ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 26 Start and Stop Definition Timing I 2 C_Data I 2 C_Data 5.7.3.6.3 Acknowledge All addresses and data words are serially transmitted to and from the optical module in 8-bit ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 in an optical module. The eighth bit of the device address is the Read/Write operation select bit. A Read operation is initiated if this bit is High and a Write operation ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Mode 1: (LED_SEL_MODE = 1): This mode is used with standard TTL (74LS599) or HCMOS (74HC599) octal shift registers with latches, providing the most general and cost- effective implementation of the ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 31 Mode 0 Clock Cycle to Data Bit Relationship LED_CLK Cycle 1 START BIT 2:3 PAD BITS 4:15 LED DATA 1-12 36:38 PAD BITS When implemented on the board with ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 30 Mode 1 Timing LED_CLK LED_DATA LED_LATCH Table 32 Mode 1 Clock Cycle to Data Bit Relationship LED_CLK Cycle LED_DATA Name 1 START BIT 2:3 PAD BITS 4:15 LED DATA ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 33 LED_DATA# Decodes (Sheet LED_DATA# 5.8.6.1 LED Signaling Behavior Operation in each mode for the decoded LED data in Table 35. 5.8.6.1.1 Fiber LED Behavior Table 34 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.8.6.1.2 Copper LED Behavior Table 35 LED Behavior (Copper Mode) Type Link LED Activity LED - Green Note: Table 33, LED_DATA# Decodes on page 180 and the LEDs are enabled in ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.9.1 Functional Description 5.9.1.1 Read Access Read access involves the following: • Detect assertion of asynchronous Read control signal and latch address • Generate internal Read strobe • Drive valid data ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 32 Write Timing Diagram - Asynchronous Interface UPX_ADD[10:0] UPX_CS_L UPX_WR_L UPX_DATA[31:0] UPX_RD_L 5.9.1.3 CPU Timing Parameters For information on the CPU interface Read and Write cycle AC timing parameters, refer ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 36 Byte Swapper Behavior UPX_BADD 32-bit [1:0] UPX_DATA_ [31:0] 00 [31:0] 01 – 10 – 11 – 8-bit mode, data is output in Little Endian format regardless of ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.10.2 Instruction Register and Supported Instructions The instruction register is a 4-bit register that enacts the boundary scan instructions. After the state machine resets, the default instruction is IDCODE. The decode ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 5.11.1 SPI3 Interface Loopback To provide a diagnostic loopback feature on the SPI3 interface possible to configure the IXF1104 MAC to loop back any data written to the IXF1104 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 34 Line Side Interface Loopback Path TX SPI3 Interface Block RX When the IXF1104 MAC is configured in this loopback mode, all of the MAC functions and features are available, ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 • +/- 50 ppm • Maximum duty cycle distortion 40/60 5.12.2 SPI3 Receive and Transmit Clocks The IXF1104 MAC transmit clock requirements include the following: • 3.3 V LVTTL drive • ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 2 5.12 Clock The IXF1104 MAC supports a single-output I interfaces. The IXF1104 MAC meets the following specifications for this clock: • 2.5 V CMOS drive • Maximum clock ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 6.0 Applications 6.1 Change Port Mode Initialization Sequence Use the change port mode initialization sequence after power-up and anytime a port is configured into or switching between fiber or copper mode, ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Enable Packet padding and CRC Appending on transmitted packets in bits 6 and 7, as needed. Set bit enable auto-negotiation. Set bit enable ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.0 Electrical Specifications Table 38 through Table 57, LED Interface AC Timing Parameters, on page 147 35, SPI3 Receive Interface Timing, on page 131 Timing, on page 147 interfaces: — SPI3 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 39 Recommended Operating Conditions Parameter Recommended supply voltage SerDes Operation Transmitting and Operating Current receiving in 1000 Mbps mode RGMII Operation Transmitting and Operating Current receiving in 1000 Mbps mode ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.1 DC Specifications The IXF1104 MAC supports the following I/O buffer types: • 2.5 V CMOS • 3.3 V LVTTL • SerDes See Section 5.1.7, Packet Buffer Dimensions, on page 76 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 41 SerDes Transmit Characteristics (Sheet Parameter Differential output impedance Receiver differential voltage requirement at center of receive eye Receiver common mode voltage range Receiver termination impedance Signal ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.1.2 RGMII Electrical Characteristics The RGMII signals (including MDIO/MDC) are based on 2.5V CMOS interface voltages, as defined by JEDEC EIA/JESD8-5 (see Table 44 RGMII Power Symbol Parameter V Output High ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Figure 35 SPI3 Receive Interface Timing RFCLK RENB RDAT[31:0] RPRY RMOD RSOP REOP RERR RVAL RSX Table 45 SPI3 Receive Interface Signal Parameters (Sheet Symbol – RFCLK frequency ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 45 SPI3 Receive Interface Signal Parameters (Sheet Symbol TPreop RFCLK High to REOP valid TPrmod RFCLK High to RMOD valid TPrerr RFCLK High to RERR valid TPrval ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.2.2 Transmit Interface Timing Figure 36 and Table 46 Figure 36 SPI3 Transmit Interface Timing TFCLK TENB TDAT[31:0] TPRTY TMOD[1:0] TSOP TEOP TERR TADR TSX DTPA STPA PTPA ® Cortina Systems ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 46 SPI3 Transmit Interface Signal Parameters Symbol – TFCLK frequency – TFCLK duty cycle TStenb TENB setup time to TFCLK THtenb TENB hold time to TFCLK TStdat TDAT[31:0] setup time ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.3 RGMII AC Timing Specification Figure 37 and Table 47 Figure 37 RGMII Interface Timing (at Transmitter) TD[3:0] TX_CTL[n] (at Receiver) (at Transmitter) RD[3:0] RX_CTL (at Receiver) Table 47 RGMII Interface ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.4 GMII AC Timing Specification 7.4.1 1000 Base-T Operation Figure 38 and Figure 39 7.4.1.1 1000 BASE-T Transmit Interface Figure 38 1000BASE-T Transmit Interface Timing GTX_CLK TXEn TXD[7:0] TXER CPS Table ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.4.1.2 1000BASE-T Receive Interface Figure 39 1000BASE-T Receive Interface Timing RX_CLK RXDV RXD[7:0] CRS Table 49 GMII 1000BASE-T Receive Signal Parameters Symbol t1 RXD[7:0], RX_DV, RXER Setup to Rx_CLK High t2 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.5 SerDes AC Timing Specification Figure 40 SerDes Timing Diagram Table 50 SerDes Timing Parameters Symbol Tt Transmit eye width Rt Receiver eye width Tv Transmit amplitude Rv Receiver amplitude ® ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.6 MDIO AC Timing Specification The MDIO Interface on the IXF1104 MAC can operate in two modes – low-speed and high- speed. In low-speed mode, the MDC clock signal operates at ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.6.3 MDIO AC Timing Figure 43 MDIO Write Timing Diagram MDC MDIO Figure 44 MDIO Read Timing Diagram MDC MDIO Table 51 MDIO Timing Parameters Parameter MDIO Setup before MDC. MDIO ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.7 Optical Module and I 2 7.7 Interface Timing Figure 45 and Figure 46 Interface AC timing characteristics. Figure 45 Bus Timing Diagram I 2 C_Clk t HD.STA I ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 2 Table Timing Characteristics (Sheet Symbol t Data in hold time HD.DAT t Data in setup time SU.DAT t Inputs rise time R t ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.8.2 CPU Interface Write Cycle AC Timing Figure 48 CPU Interface Write Cycle AC Timing UPX_ADD[10:0] UPX_CS_L UPX_WR_L UPX_DATA[31:0] UPX_RD_L Table 53 CPU Interface AC Signal Parameters Symbol Tcas Address, chip ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.9 Transmit Pause Control AC Timing Specification Figure 49 and Table 54 interface operates as an asynchronous interface relative to the main system clock (CLK125). There is, however, a relationship between ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.10 JTAG AC Timing Specification Figure 50 and Table 55 Figure 50 JTAG AC Timing Table 55 JTAG AC Timing Parameters Symbol Tjc TCLK cycle time Tjh TCLK High time Tjl ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.11 System AC Timing Specification Figure 51 and Table 56 Figure 51 System Reset AC Timing Table 56 System Reset AC Timing Parameters Symbol Trw Reset pulse width Trt Reset recovery ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 7.12 LED AC Timing Specification Figure 52 and Table 57 Figure 52 LED AC Interface Timing LED_CLK LED_DATA LED_LATCH Table 57 LED Interface AC Timing Parameters Symbol Tcyc LED_CLK cycle time ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 8.0 Register Set The registers shown in this section provide access for configuration, alarm monitoring, and control of the chip. Table 58, MAC Control Registers ($ Port Index + Offset), on ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 The address vector for the IXF1104 MAC is 11 bits wide. This allows for 7 bits of port- specific access and a 4-bit vector to address each port and all global ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 58 MAC Control Registers ($ Port Index + Offset) (Sheet Register Discard Unknown Control Frame ($ Port_Index + 0x15) RX Config Word ($ Port_Index + 0x16) TX ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 60 MAC TX Statistics Registers ($ Port Index + Offset) Register OctetsTransmittedOK OctetsTransmittedBad TxUCPkts TxMCPkts TxBCPkts TxPkts64Octets TxPkts65to127Octets TxPkts128to255Octets TxPkts256to511Octets TxPkts512to1023Octets TxPkts1024to1518Octets TxPkts1519toMaxOctets TxDeferred TxTotalCollisions TxSingleCollisions TxMultipleCollisions TxLateCollisions TxExcessiveCollisionErrors TxExcessiveDeferralErrors ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 61 PHY Autoscan Registers ($ Port Index + Offset) (Sheet Register Auto-Negotiation Expansion ($ Port Index + 0x66) Auto-Negotiation Next Page Transmit ($ Port Index + 0x67) ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 63 RX FIFO Registers ($ 0x580 - 0x5BF) (Sheet Register RX FIFO Errored Frame Drop Enable ($0x59F) RX FIFO Overflow Event ($0x5A0) Reserved RX FIFO Errored Frame ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 64 TX FIFO Registers ($ 0x600 - 0x63E) (Sheet Register TX FIFO Overflow Frame Drop Counter Port 1 TX FIFO Overflow Frame Drop Counter Port 2 TX ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 67 SerDes Registers ($ 0x780 - 0x798) (Sheet Register RX Signal Detect Level Ports ($0x793) Clock and Interface Mode Change Enable Ports 0 - ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 70 Desired Duplex ($ Port_Index + 0x02) Bit Name Register Description: Chooses between half-duplex and full-duplex operation in RGMII 100 Mbps or 10 Mbps mode only. This register must be ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table Timer Value ($ Port_Index + 0x07) Name The 16-bit pause length inserted in the flow FC TX Timer control pause frame sent to the receiving Value station. ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 77 IPG Receive Time 2 ($ Port_Index + 0x0B) Name IPG Receive Time Read Only, No clear on Read Read, Clear on Read; W ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 80 Max Frame Size (Addr: Port_Index + 0x0F) Name This is a 14-bit value configuring the maximum frame size the MAC can receive or transmit without activating any error counters, ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 83 FC Enable ($ Port_Index + 0x12) Bit Name Register Description: Indicates which flow control mode is used for the RX and TX MAC. 31:3 Reserved 2 TX HDFC 1 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 85 Short Runts Threshold ($ Port_Index + 0x14) Name The 5-bit configuration holds the value in bytes, which applies to the threshold in determining between runts and short. The bits ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 87 RX Config Word ($ Port_Index + 0x16) (Sheet Bit Name 19 RX Config 18 Config Changed 17 Invalid Word 16 Carrier Sense 15 Next Page 14 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 88 TX Config Word ($ Port_Index + 0x17) (Sheet Bit Name 2 13:12 Remote Fault [1:0] 11:9 Reserved 8 Asym Pause 7 Sym Pause 6 Half Duplex ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 90 RX Packet Filter Control ($ Port_Index + 0x19) (Sheet Bit Name Register Description: This register allows for specific packet types to be marked for filtering and ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 90 RX Packet Filter Control ($ Port_Index + 0x19) (Sheet Bit Name 2 B/Cast Drop En 1 M/Cast Match En 0 U/Cast Match ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 92 MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet Name Description Counts the bytes received in all legal frames, including all bytes from the ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 92 MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet Name Description The total number of packets received (including RxPkts256to511 bad packets) that were 256-511 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 92 MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet Name Description Frames bigger than the maximum allowed, with both OK CRC and the integral ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 92 MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet Name Description The total number of packets received that are less than 64 octets in ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 8.4.3 MAC TX Statistics Register Overview The MAC TX Statistics registers contain all the MAC transmit statistic counters and are cleared when read. The software must poll these registers to accumulate ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 93 MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet Name TxBCPkts TxPkts64Octets Txpkts65to127Octets Txpkts128to255Octets Txpkts256to511Octets Txpkts512to1023Octets Txpkts1024to1518Octets Txpkts1519toMaxOctets TxDeferred TxTotalCollisions Read Only, No ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 93 MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet Name TxSingleCollisions TxMultipleCollisions TxLateCollisions TxExcessiveCollisionErrors TxExcessiveDeferralErrors TxExcessiveLengthDrop TxUnderrun TxTagged Read Only, No clear on ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 93 MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet Name TxCRCError TxPauseFrames TxFlowControlCollisions Send Read Only, No clear on Read Read, ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 94 PHY Control ($ Port Index + 0x60) (Sheet Bit Name 10 Isolate Restart 9 Auto-Negotiation 8 Duplex Mode 7 Collision Test Speed Selection 6 1000 Mbps ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 95 PHY Status ($ Port Index + 0x61) (Sheet Bit Name 100BASE-T2 9 Half-Duplex 8 Extended Status 7 Reserved MF Preamble 6 Suppression 5 Reserved 4 Remote ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 97 PHY Identification 2 ($ Port Index + 0x63) (Sheet Bit Name 15:10 PHY ID Number 9:4 Manufacturer’s Model Manufacturer’s 3:0 Revision Number Read ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 98 Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet Bit Name 10BASE-T 6 Full-Duplex 10BASE-T 5 Half-Duplex Selector Field, 4:0 S[4: Read Only; RR ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 99 Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65) (Sheet Bit Name 100BASE-TX 8 Full-Duplex 100BASE-TX 7 Half-Duplex 10BASE-T 6 Full-Duplex 10BASE-T 5 Half-Duplex ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 100 Auto-Negotiation Expansion ($ Port Index + 0x66) (Continued) (Sheet Bit Name 2 Next Page Able 1 Page Received Link Partner Auto- 0 Negotiation Able 1. RO ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 102 Port Enable ($0x500) Bit Name Register Description: A control register for each port in the IXF1104 MAC. Port ID = bit position in the register. To make a port ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 104 Link LED Enable ($0x502) Bit Name Register Description: Per port bit should be set upon detection of link to enable proper operation of the link LEDs. 31:4 Reserved 3 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 106 MDIO Soft Reset ($0x506) Bit Name Register Description: Software-activated reset of the MDIO module. The MDIO controller inside of the IXF1104 is reset by bit 0. The IXF1104 MDIO ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 109 LED Flash Rate ($0x50A) Bit Name Register Description: Global selection of LED flash rate. 31:3 Reserved LED Flash Rate 2:0 Control Read Only, No clear on ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 111 JTAG ID ($0x50C) Bit Name Register Description: The value of this register follows the same scheme as the device identification register found in the IEEE 1149.1 specification. The upper ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 113 RX FIFO High Watermark Port 1 ($0x581) Bit Name Register Description: The default value of 0x0E6 represents 230 eight-byte locations. This equates to 1840 bytes of data. A unit ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 116 RX FIFO Low Watermark Port 0 ($0x58A) Bit Name Register Description: The default value of 0x072 represents 114 eight-byte locations. This equates to 912 bytes of data. A unit ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 119 RX FIFO Low Watermark Port 3 ($0x58D) Bit Name Register Description: The default value of 0x072 represents 114 eight-byte locations. This equates to 912 bytes of data. A unit ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 121 RX FIFO Port Reset ($0x59E) (Sheet Bit Name Reset RX FIFO for 2 Port 2 Reset RX FIFO for 1 Port 1 Reset RX FIFO for ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 123 RX FIFO Overflow Event ($0x5A0) Bit Name Register Description: This register provides a status if a FIFO-full situation occurs (for example, a FIFO overflow). The bit position equals the ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 124 RX FIFO Errored Frame Drop Counter Ports ($0x5A2 - 0x5A5) (Sheet Name RX FIFO Errored Frame Drop Counter on Port 2 RX FIFO ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 126 RX FIFO Padding and CRC Strip Enable ($0x5B3) Bit Name Register Description: This control register enables to pre-pend every packet with two extra bytes and also enables the CRC ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 127 RX FIFO Transfer Threshold Port 0 ($0x5B8) (Sheet 31:12 Reserved RX FIFO Transfer 11:0 Threshold - Port Read Only, No clear on ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 130 RX FIFO Transfer Threshold Port 3 ($0x5BB) Bit Name Register Description: RX FIFO transfer threshold for port 3 in 8-byte location. 31:12 Reserved RX FIFO Transfer 11:0 Threshold - ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 131 TX FIFO High Watermark Ports ($0x600 – 0x603) (Sheet Name Description High watermark for TX FIFO Port 1. The default value of 0x3E0 ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 132 TX FIFO Low Watermark Register Ports ($0x60A – 0x60D) Name Description Low watermark for TX FIFO Port 0. The default value of 0x0D0 represents 208 8-byte ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 133 TX FIFO MAC Threshold Register Ports ($0x614 – 0x617) Name Description MAC threshold for TX FIFO Port 0. The default value of 0x1BE represents 446 8-byte ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 134 TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) Bit Name Register Description: TX FIFO Out of Sequence Event: These register bits provide status information, and indicate if out-of-sequence data has ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 135 Loop RX Data to TX FIFO (Line-Side Loopback) Ports ($0x61F) Bit Name Register Description: This register enables data received from the line-side receive interface through the ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 137 TX FIFO Overflow Frame Drop Counter Ports ($0x621 – 0x624) Name Description When TX FIFO on Port 0 becomes full or TX FIFO overflow reset, the ...
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IXF1104 MAC Datasheet 278757, Revision 13.2 17 September 2008 Table 138 TX FIFO Errored Frame Drop Counter Ports ($0x625 – 0x629) Name Description This register provides the number of packets dropped by the TX FIFO due to ...