WPIXF1104BE.B1-993991 Cortina Systems Inc, WPIXF1104BE.B1-993991 Datasheet - Page 200

• Manufacturer Part Number: WPIXF1104BE.B1-993991
• Description: IC ETH MAC SPI3 4-PORT 552-FCBGA
• Manufacturer: Cortina Systems Inc

Specifications of WPIXF1104BE.B1-993991

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 1008-1045

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 138
Table 139
Cortina Systems
TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)
TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D – 0x630) (Sheet 1 of 2)
®
Name
TX FIFO errored
frame drop counter
on Port 0
TX FIFO errored
frame drop counter
on Port 1
TX FIFO errored
frame drop counter
on Port 2
TX FIFO errored
frame drop counter
on Port 3
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Name
Occupancy for Tx
FIFO Port 0
Occupancy for Tx
FIFO Port 1
IXF1104 4-Port Gigabit Ethernet Media Access Controller
clear; R/W/C = Read/Write, Clear on Write
Description
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
Note:
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
Note:
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
Note:
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
Note:
Description
This register gives the Occupancy for TX FIFO
Port 0. This is a Read only register
This register gives the Occupancy for TX FIFO
Port 1. This is a Read only register
This register is cleared on Read.
This register is cleared on Read.
This register is cleared on Read.
This register is cleared on Read.
Address
0x625
0x626
0x627
0x628
Address
0x62D
0x62E
Type
Type
R
R
R
R
R
R
*
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Default
Default
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