WPIXF1104BE.B1-993991 Cortina Systems Inc, WPIXF1104BE.B1-993991 Datasheet - Page 212

• Manufacturer Part Number: WPIXF1104BE.B1-993991
• Description: IC ETH MAC SPI3 4-PORT 552-FCBGA
• Manufacturer: Cortina Systems Inc

Specifications of WPIXF1104BE.B1-993991

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 1008-1045

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 154
Table 155
Cortina Systems
I
I
®
Register Description: This register controls and monitors the interface to the optical modules
when used in fiber mode.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Register Description: These registers hold data bytes that are read and written using the I
interface to Optical Module Interfaces connected to each port of the IXF1104 4-Port Gigabit
Ethernet Media Access Controller.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
2
31:29
19:18
17:16
14:11
2
31:24
23:16
10:0
15:8
Bit
Bit
7:0
C Control Ports 0 - 3 ($0x79B)
C Data Ports 0 - 3 ($0x79F)
IXF1104 4-Port Gigabit Ethernet Media Access Controller
28
27
26
25
24
23
22
21
20
15
clear; R/W/C = Read/Write, Clear on Write
clear; R/W/C = Read/Write, Clear on Write
Name
Reserved
Port address Err (R)
wp_err
no_ack_err
I
I
Reserved
write_complete
Reserved
Read_complete
Reserved
Port Select
Read/Write
Device ID
Register Address
Name
Reserved
Write Data
Reserved
Read Data
2
2
C_enable
C_start
Reserved
Port addressing error.
An attempt to write to the protected E
Enable the I
Reserved
Bit is asserted when write access is complete.
Reserved
Bit asserted when read access is complete.
Reserved
0 = Write transaction
1 = Read transaction
Most-significant four bits of device address field.
Bits 10:8 select the least-significant three bits of
the device address field
Bits 7:0 select the word/register address
Reserved
Reserved
Bit 7 = MSB, Bit 0 = LSB
Data read from the Optical Module Interface.
Description
occurred.
This bit is set to 1 when a write and subsequent
read from an Optical Module Interface has failed.
Use this signal to validate the data being read.
Data is only valid if this bit is equal to zero.
Start the I
Selects the port for which the I
targeted. Valid range is 0 to 3.
Description
Bit 23=MSB, Bit 16 = LSB
Data to be written to the Optical Module Interface.
2
C transfer.
2
C block.
2
C transaction is
2
PROM has
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
R
R
R
R
R
2
C
1
1
0x00000000
0x00000000
Default
Default
0x000
0X00
0X00
0x00
0x00
0x0
0x0
00
0
0
0
0
0
0
0
0
0
0
0
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