OM6274 NXP Semiconductors, OM6274 Datasheet - Page 7

• Manufacturer Part Number: OM6274
• Description: Interface Modules & Development Tools I2C to SPI Master Bridge Demoboard
• Manufacturer: NXP Semiconductors

Specifications of OM6274

• Interface Type: I2C, SPI
• Data Bus Width: 8 bit
• For Use With/related Products: SC18IS602IPW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
SC18IS602_602B_603_4
Product data sheet
7.1.5 Configure SPI Interface - Function ID F0h
The SPI hardware operating mode, data direction, and frequency can be changed by
sending a ‘Configure SPI Interface’ command to the I
After the SC18IS602/602B/603 address is transmitted on the bus, the Configure SPI
Interface Function ID (F0h) is sent followed by a byte which will define the SPI
communications.
The Clock Phase bit (CPHA) allows the user to set the edges for sampling and changing
data. The Clock Polarity bit (CPOL) allows the user to set the clock polarity.
Figure 21
Table 4.
Table 5.
Bit
Symbol
Reset
Bit
7:6
5
4
3:2
1:0
Fig 10. Configure SPI Interface
show the different settings of Clock Phase bit CPHA.
Symbol
-
ORDER
-
MODE1:MODE0 Mode selection
F1:F0
Configure SPI Interface (F0h) bit allocation
Configure SPI Interface (F0h) bit description
X
X
7
S
SLAVE ADDRESS
Rev. 04 — 11 March 2008
6
X
X
Description
reserved
When logic 0, the MSB of the data word is transmitted first.
If logic 1, the LSB of the data word is transmitted first.
reserved
SPI clock rate
SC18IS602/602B:
SC18IS603:
00 - SPICLK LOW when idle; data clocked in on leading edge
(CPOL = 0, CPHA = 0)
01 - SPICLK LOW when idle; data clocked in on trailing edge
(CPOL = 0, CPHA = 1)
10 - SPICLK HIGH when idle; data clocked in on trailing edge
(CPOL = 1, CPHA = 0)
11 - SPICLK HIGH when idle; data clocked in on leading edge
(CPOL = 1, CPHA = 1)
00 - 1843 kHz
01 - 461 kHz
10 - 115 kHz
11 - 58 kHz
00 -
01 -
10 -
11 -
ORDER
fosc
fosc
fosc
fosc
5
0
4
16
64
128
W
A
X
X
4
SC18IS602/602B/603
F0h
MODE1
2
A
3
0
C-bus.
DATA
MODE0
2
0
002aac450
I
2
A
C-bus to SPI bridge
P
© NXP B.V. 2008. All rights reserved.
F1
1
0
Figure 20
F0
0
0
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and