WM8351GEB/V Wolfson Microelectronics, WM8351GEB/V Datasheet - Page 206

• Manufacturer Part Number: WM8351GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8351GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8351
w
R33 (21h)
Interrupt Status
1 Mask
Table 151 Charger Interrupts
24.3.11 USB INTERRUPTS
The first-level USB_INT interrupt comprises one second-level interrupt for the USB limit switch. This
status bit is in Register R26 and its mask bit is in Register R34, as defined in Table 152.
R26 (1Ah)
Interrupt
Status 2
R34 (22h)
Interrupt
Status 2 Mask
Table 152 USB Interrupt
ADDRESS
ADDRESS
15:9
BIT
BIT
2:0
10
10
2
1
0
USB_LIMIT_EINT
IM_USB_LIMIT_EINT
CHG_VBATT_LT_3P9_EINT
CHG_VBATT_LT_3P1_EINT
CHG_VBATT_LT_2P85_EIN
T
“IM_” + name of respective
bit in R25
LABEL
LABEL
USB Limit Switch interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
When IM_USB_LIMIT_EINT is set to 1,
then USB_LIMIT_EINT in R26 does not
trigger an USB_INT interrupt when set.
The default value is 0 (unmasked).
Battery Voltage < 3.9 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Battery voltage < 3.1 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Battery voltage < 2.85 interrupt.
(Rising Edge triggered)
Note: This bit is cleared once read.
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Each bit in R33 enables or masks the
corresponding bit in R25. The default
value for these bits is 0 (unmasked).
PD, March 2010, Rev 4.2
DESCRIPTION
DESCRIPTION
Production Data
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