WM8351GEB/V Wolfson Microelectronics, WM8351GEB/V Datasheet - Page 91

• Manufacturer Part Number: WM8351GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8351GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
R114 (72h)
Audio
Interface
ADC
Control
R115 (73h)
Audio
Interface
DAC
Control
Table 45 Selecting the Audio Data Format
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 50 Left Justified Audio Interface (assuming n-bit word length)
ADDRESS
DACDAT/
ADCDAT
LRCLK
BCLK
BIT
7
6
5
4
3
7
6
5
4
3
MSB
1
2
AIFADC_PD
AIFADCL_SRC
AIFADCR_SRC
AIFADC_TDM_
CHAN
AIFADC_TDM
AIFDAC_PD
DACL_SRC
DACR_SRC
AIFDAC_TDM_
CHAN
AIFDAC_TDM
3
Input Word Length (WL)
LABEL
LEFT CHANNEL
n-2
n-1
LSB
n
DEFAULT
(I
2
0
0
1
0
0
0
0
1
0
0
S)
1/fs
1
00 = Right Justified
01 = Left Justified
10 = I
11 = DSP / PCM mode
Note - see Section 13.11 for the
selection of 8-bit mode.
Enables a pull down on ADC data pin
0 = disabled
1 = enabled
Selects Left channel ADC output.
0 = ADC Left channel
1 = ADC Right channel
Selects Right channel ADC output.
0 = ADC Left channel
1 = ADC Right channel
ADCDAT TDM Channel Select
0 = ADCDAT outputs data on slot 0
1 = ADCDAT output data on slot 1
ADC TDM Enable
0 = Normal ADCDAT operation
1 = TDM enabled on ADCDAT
Enables a pull down on DAC data pin
0 = disabled
1 = enabled
Selects Left channel DAC input.
0 = DAC Left channel
1 = DAC Right channel
Selects Right channel DAC input.
0 = DAC Left channel
1 = DAC Right channel
DACDAT TDM Channel Select
0 = DACDAT outputs data on slot 0
1 = DACDAT output data on slot 1
DAC TDM Enable
0 = Normal DACDAT operation
1 = TDM enabled on DACDAT
2
3
2
S
RIGHT CHANNEL
DESCRIPTION
n-2
n-1
PD, March 2010, Rev 4.2
n
WM8351
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