WM8351GEB/V Wolfson Microelectronics, WM8351GEB/V Datasheet - Page 312
WM8351GEB/V
Manufacturer Part Number
WM8351GEB/V
Description
Audio CODECs Audio CODEC plus pwr management
Manufacturer
Wolfson Microelectronics
Datasheet
1.WM8351GEBV.pdf
(328 pages)
Specifications of WM8351GEB/V
Number Of Adc Inputs
2
Number Of Dac Outputs
2
Conversion Rate
48 KSPS
Interface Type
Serial (2-Wire, 3-Wire, 4-Wire)
Resolution
12 bit
Operating Supply Voltage
3.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
BGA
Minimum Operating Temperature
- 25 C
Number Of Channels
2 ADC/2 DAC
Supply Current
260 uA
Thd Plus Noise
- 83 dB
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
8
No. Of Output Channels
6
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
95dB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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WM8351
Register E5h Supply overrides/status 2
w
REGISTER
ADDRESS
R230 (E6h)
REGISTER
ADDRESS
GPIO Pin
Status
BIT
15
14
13
12
11
10
BIT
9
8
1
0
UNDV_DC2_OVRDE
UNDV_DC1_OVRDE
GP12_LVL
GP11_LVL
GP10_LVL
GP9_LVL
GP8_LVL
LABEL
1
1
1
LABEL
DEFAULT
1
1
1
0
0
0
0
0
DEFAULT
0
0
Unused
Never reset.
Unused
Never reset.
Unused
Never reset.
Logic level of GPIO12 pin
Input-
Reads the logic level of GPIO pin
Writing ‘0’ clears GP12_EINT
Output-
Write sets the value to drive the GPIO pin
Logic level of GPIO11 pin
Input-
Reads the logic level of GPIO pin
Writing ‘0’ clears GP11_EINT
Output-
Write sets the value to drive the GPIO pin
Logic level of GPIO10 pin
Input-
Reads the logic level of GPIO pin
Writing ‘0’ clears GP10_EINT
Output-
Write sets the value to drive the GPIO pin
Logic level of GPIO9 pin
Input-
Reads the logic level of GPIO pin
Writing ‘0’ clears GP9_EINT
Output-
Write sets the value to drive the GPIO pin
Logic level of GPIO8 pin
Input-
Reads the logic level of GPIO pin
Writing ‘0’ clears GP8_EINT
Output-
Write sets the value to drive the GPIO pin
CONVERTER_UV_OVRDE bit is set to 1.
Readback of the raw signal value.
Allow direct control of this signal's input to the
debounce logic when the
CONVERTER_UV_OVRDE bit is set to 1.
Readback of the raw signal value.
Allow direct control of this signal's input to the
debounce logic when the
CONVERTER_UV_OVRDE bit is set to 1.
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
REFER TO
REFER TO
Production Data
312
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