PIC18F6680-I/L Microchip Technology, PIC18F6680-I/L Datasheet - Page 130

• Manufacturer Part Number: PIC18F6680-I/L
• Description: Microcontrollers (MCU) 64KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6680-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
10.2
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory mapped.
Read-modify-write operations on the LATB register read
and write the latched output value for PORTB.
EXAMPLE 10-2:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB3:RB0) are the external
interrupt pins, INT3 through INT0. In order to use these
pins as external interrupts, the corresponding TRISB
bit must be set to ‘1’.
The other four PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are OR’ed together to generate the RB port
change interrupt with flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
DS30491C-page 128
CLRF
CLRF
MOVLW
MOVWF
Note:
Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
Clear flag bit RBIF.
PORTB, TRISB and LATB
Registers
PORTB
LATB
0CFh
TRISB
On a Power-on Reset, these pins are
configured as digital inputs.
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
INITIALIZING PORTB
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For PIC18FXX85 devices, RB3 can be configured by the
configuration bit, CCP2MX, as the alternate peripheral
pin for the CCP2 module. This is only available when the
device is configured in Microprocessor, Microprocessor
with Boot Block, or Extended Microcontroller Operating
modes.
The RB5 pin is used as the LVP programming pin.
When the LVP configuration bit is programmed, this pin
loses the I/O function and becomes a programming test
function.
FIGURE 10-5:
Note 1:
Note:
RB7:RB5 in Serial Programming Mode
RBPU
Data Bus
or PORTB
WR TRISB
RD TRISB
RD LATB
RD PORTB
Set RBIF
WR LATB
From other
RB7:RB4 pins
2:
(2)
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
When LVP is enabled, the weak pull-up on
RB5 is disabled.
TRIS Latch
Data Latch
D
D
CK
CK
BLOCK DIAGRAM OF
RB7:RB4 PINS
Q
Q
 2004 Microchip Technology Inc.
Q
Q
Latch
EN
D
EN
D
DD
TTL
Input
Buffer
RD PORTB
and V
V
P
DD
SS
Weak
Pull-up
I/O pin
Buffer
Q1
.
Q3
ST
(1)